Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-28
2004-03-23
Niebling, John F (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S019000, C257S336000
Reexamination Certificate
active
06710407
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the structure of a filed effect transistor and, more particularly, to a semiconductor device having a field effect transistor with a multi-layered gate electrode formed from a silicon-germanium layer, a polysilicon layer and a refractory metal silicide layer.
DESCRIPTION OF THE RELATED ART
Various sorts of integrated circuits are fabricated on semiconductor substrates, and p-channel type field effect transistors and n-channel type field effect transistors are major circuit components of the integrated circuits. The p-channel type field effect transistors and n-channel type field effect transistors have been scaled down for enhancing the integration density of the circuit components. This results in the miniature electrode and extremely thin gate insulating layer. However, when the gate electrode is miniaturized, the short channel effect tends to occur in the field effect transistor due to the narrow gate width.
A countermeasure against the short channel effect is introduction of dopant impurity, which is opposite to the channel conductivity, into the gate electrode. Boron is, by way of example, introduced into the polysilicon gate electrodes of the p-channel type field effect transistors, and arsenic or phosphorous is introduced into the polysilicon gate electrodes of the n-channel type field effect transistors.
The opposite dopant impurity is introduced as follows. First, insulating material is grown on the major surface of the silicon substrate, and polysilicon is further grown on the insulating layer. The insulating layer serves as the gate insulating layers of the field effect transistors, and the polysilicon layer is patterned into polysilicon strips for the gate electrodes. P-type dopant impurity is concurrently ion implanted into surface portions of the silicon substrate and the polysilicon strips in the self-aligned manner so that the p-type doped polysilicon strips are obtained together with the p-type doped silicon regions. Furthermore, n-type dopant impurity is concurrently ion implanted into other surface portions of the silicon substrate and the remaining polysilicon strips in the self-aligned manner so that the n-type doped polysilicon strips are obtained together with the n-type doped silicon regions.
After the ion-implantation, the p-type doped silicon regions, p-type doped polysilicon strips, n-type doped silicon regions and n-type doped polysilicon strips are subjected to a heat treatment. While the thermal energy is being applied to the silicon substrate, the p-type dopant impurity and n-type dopant impurity are activated, and p-type source/drain regions, p-type gate electrodes, n-type source/drain regions and n-type gate electrodes are produced from the p-type doped silicon regions, p-type doped polysilicon strips, n-type doped silicon regions and n-type doped polysilicon strips, respectively.
However, a problem is encountered in the prior art semiconductor device in that the p-channel type field effect transistors exhibit transistor characteristics not so high as those expected. This is because of the fact that the amount of thermal energy to be required for activation of dopant impurity is different between the born and the arsenic/phosphorous.
The manufacturer is assumed to adjust the heat treatment to a time period proper to activate the arsenic or phosphorous. Although the thermal energy is much enough to activate the arsenic or phosphorous, the thermal energy is too little to activate the boron, and leaves a substantial amount of boron inactive. The inactive boron is left at the boundary between the gate insulating layer and the gate electrode. When the gate electrode is biased, a depletion layer extends from the boundary into the gate electrode, and the depletion layer makes the threshold varied.
On the other hand, if the manufacturer adjusts the heat treatment to a time period long enough to active the boron, the thermal energy is much enough to activate the boron as well as the arsenic/phosphorous. However, the arsenic/phosphorous are diffused over target profiles of the source/drain regions.
Thus, there is a trade-off in the activation between the boron and the arsenic/phosphorous. A countermeasure against the problem is disclosed in Japanese Patent Application laid-open No. 2000-150669. Introduction of germanium is taught in the Japanese Patent Application laid-open. The germanium enhances the activation of boron so that the gate electrode is prevented from the depletion layer.
FIG. 1A
shows the p-channel type field effect transistor. The prior art p-channel type field effect transistor is fabricated on a silicon substrate (not shown). An epitaxial layer is grown on the silicon substrate, and an n-type well
4
is formed in a surface portion of the epitaxial layer. An isolating region
5
is formed in the n-type well
4
, and defines an active region assigned to the prior art p-channel type field effect transistor in the n-type well
4
. A gate insulating layer
6
is grown on a surface portion of the active region, and a gate electrode
7
is fabricated on the gate insulating layer
6
.
The gate electrode
7
has a multi-layered structure, and boron is doped in the multi-layered structure. The multi-layered structure consists of amorphous silicon layer
711
on the gate insulating layer
6
, a silicon-germanium layer
712
laminated on the amorphous silicon layer
711
, a polysilicon layer
713
laminated on the silicon-germanium layer
712
and a cobalt silicide layer
12
self-aligned with the polysilicon layer
713
. Insulating side walls
10
are formed on the side surfaces of the multi-layered structure.
On both sides of the gate electrode
7
are formed heavily-doped p-type source/drain regions
9
which are overlaid with cobalt silicide layers
12
in a self-aligned manner. The heavily-doped p-type source/drain regions
9
are doped with boron.
The germanium in the silicon-germanium layer
712
enhances the activation of the boron doped in the silicon. The activated boron is so much at the boundary between the gate insulating layer and the multi-layered structure that the depletion layer is less developed. Thus, the germanium in the gate electrode
7
restricts the undesirable fluctuation of the threshold.
Another advantage is taught in the Japanese Patent Application laid-open. The silicon germanium layer decelerates the diffusion of boron so that the boron is less diffused into the channel region.
The present inventor confirmed the advantages of the prior art gate structure. The germanium surely enhanced the activation of the boron. Nevertheless, the present inventor noticed that the germanium was an obstacle against the silicidation. While the boron-implanted layers are being heated, the cobalt reacted with the silicon, and the cobalt silicide was grown on the polysilicon layer
713
and the source/drain regions
9
in the self-aligned manner. The germanium was diffused in the heat treatment, and reached the boundary between the polysilicon layer
713
and the cobalt layer. The germanium less reacted with the cobalt, and caused the cobalt silicide to be coagulated as shown in FIG.
1
B. This means that the cobalt silicide layer was not continuously formed on the polysilicon layer
713
. The manufacturer expected the cobalt silicide layer to reduce the resistance along the signal lines. However, the coagulated cobalt silicide caused the signal line to have large resistance. Thus, the germanium spoiled the self-aligned silicide, i. e., salicide structure.
The present inventor carried out experiments to see whether or not the coagulation occurred on other salicide structures. The present inventor fabricated the prior art p-channel type field effect transistors where the cobalt was replaced with titanium or nickel. The titanium silicide and nickel silicide were also coagulated on the gate electrodes.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a semiconductor device, a field effect transistor of which includes a germanium containing gat
Lindsay Jr. Walter L.
NEC Electronics Corporation
Niebling John F
Young & Thompson
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