Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-11-02
2004-04-20
Lefkowitz, Sumati (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S315000, C379S221080, C379S221110, C370S216000, C714S005110, C714S010000
Reexamination Certificate
active
06725312
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the field of computers, and more particularly to the communication buses used for communications within a computer.
BACKGROUND OF THE INVENTION
Communications within a computer take place along pathways known as buses. It can be appreciated that it is difficult, if not impossible, to design a bus that meets all the requirements that might be placed on it regardless of the type of computer with which it is associated. Some of these requirements include high speed, the ability to handle large amounts of data (typically produced by so called ‘multi-media’ devices), the ability to communicate with devices in remote locations, the ability to provide high reliability communications, compatibility with a large array of peripheral devices and be low cost. This list is by no means exhaustive but it indicates the types of competing, sometimes mutually exclusive requirements placed on buses.
The ISA (Industry Standard Architecture) bus was introduced by IBM in 1984. This 16-bit/8-MHz bus became the industry standard in computers. However, difficulties began to arise when 32 bit processors were introduced. Such processors along with the introduction of peripheral devices that generate large amounts of data made this a narrow and slow means of communication. The increasing requirements placed on buses required that a new, more flexible architecture be introduced.
U.S. Pat. No. 5,263,139, issued on Nov. 16, 1993 to Testa et. al., discloses a multiple bus architecture that allows flexible communications between a processor or processors and other systems.
FIG. 1
of this application shows a block diagram representation of such a bus architecture. Multiple buses
106
,
108
and
110
are connected to a main system interconnect bus
112
. Bus
108
connects the processor(s)
100
, bus
106
is, for example, a SCSI bus that connects external devices
102
and bus
110
provides communications for remote devices
104
. The patent proposes bus
110
could be an ISDN connection. These buses provide specialized communications for the various systems allowing performance to be optimized for increased data throughput.
The speed of data transfer between the processor and subsystems can be increased by reducing the length of the transmission path i.e. the central processor and peripheral boards are located within a defined, short distance of one another, thereby limiting delays due to transmission length. This idea is the basis for ‘local buses’. The current standard in local buses, and buses in general, is the Peripheral Component Interconnect (PCI) bus. The PCI bus is a local bus that was introduced by Intel in 1991. The specifications of a PCI bus can be found in the Peripheral Component Interconnect (PCI) Local Bus Specification Revision 2.0, dated Apr. 30, 1993 (“the PCI Specification”) published by the PCI Special Interest Group.
FIG. 2
shows a simplified block diagram representation of an implementation of a PCI bus. The PCI bus
204
forms a one-to-many connection between the CPU
200
and the peripheral components
202
, which are located in the same chassis.
The PCI bus is installed on most new desktop computers. It transmits 32 bits at a time in a 124-pin connection (the extra pins are for power supply and grounding) and 64 bits in a 188-pin connection in an expanded implementation. PCI buses use all active paths to transmit both address and data signals, sending the address on one clock cycle and data on the next. Burst data can be sent starting with an address on the first cycle and a sequence of data transmissions on a certain number of successive cycles.
PCI buses are often used for three purposes. First, they can be used to expand the capabilities of a computer's motherboard. In this scenario expansion boards are inserted in slots on the motherboard that are connected to the PCI bus. The Central Processing Unit (CPU) of the motherboard can then access the circuitry of the expansion board. Second, the PCI bus can be used to add processing power to a computer system. In this scenario, the expansion boards that are inserted in the motherboard are equipped with at least one CPU. The PCI bus allows the CPU of the motherboard to communicate with the expansion CPU. Finally, it allows for a multi-CPU computer system, the PCI bus can be used by the CPUs to share resources such as memory devices.
The PCI bus has become widely implemented in computer systems. This is particularly true in the area of personal computers (PCs). This wide implementation implies that there are many components that are compliant with the PCI Specification. Computer systems that do not use these PCI compliant components are not as easy to implement.
There are some limitations of the PCI bus that while not being particularly troublesome for personal computers (PCs) are significant to industrial grade PCs used in more ‘critical’ applications. These limitations include: latencies created by the continually increasing amounts of data that can be produced by today's peripheral boards, bus reliability and susceptibility to ‘single point’ failures, and the ability to locate the peripheral boards in remote locations with respect to the system processor.
First, the issue of bus latency has become more of a concern as peripheral boards transmit larger amounts of data. In particular, multi-media devices that handle audio or visual data transmit large amounts of data that requires real time processing. During times when data is being transferred from such data intensive peripheral boards the other devices on the bus are idled. The resulting bus latency can create undesirable degradations in performance. In these cases the PCI bus becomes the ‘bottleneck’ in the computer. U.S. Pat. No. 5,682,484, issued on Oct. 28, 1997 to Lambrecht, discloses the use of a separate, dedicated, multi-media bus for data intensive devices. In one scenario control information is transmitted on the PCI bus while real time data is transferred on the multi-media bus. In an alternative embodiment a separate serial bus is used for control signals. Thus, the use of a serial bus for control signals and a multimedia bus is known.
Second, PCI buses do not provide high reliability communications. The PCI bus is a single electrical connection between the central processor and every peripheral board connected to the bus. It is a one-to-many communication bus i.e. one central processing unit to many peripheral boards. Both address and data signals are transmitted on the PCI bus, sending the address on one clock cycle and data on the next. If there is a malfunction on a peripheral board that impairs communication on the bus, the central processing unit will be prevented from communicating with every other peripheral board due to the common electrical connection. This type of bus failure is known as a ‘single point’ failure. Thus, a failure of an individual peripheral component can interrupt the communications between the system processor and other peripheral boards on the same PCI bus. Such a situation is quite undesirable in high reliability applications such as telephone switching. One approach for overcoming this problem is with the use of redundancy. The reliability requires a completely redundant system i.e. duplicate system processors, PCI buses and peripheral boards. The redundant system can be maintained as redundant or provide load sharing for the primary system. This solution consumes considerable space and is costly.
Finally, the speed of communications prescribed by the PCI Specification requires the use of a local bus. The maximum length of bus prescribed in the PCI Specification is several inches which prohibits communication with any peripheral boards that is in a remote location with respect to the central processor. U.S. Pat. No. 5,781,747 issued to Smith et. al. on Jul. 14, 1998, proposes a system for extending the distance over which communications can take place. Their proposal is schematically shown in FIG.
3
. The CPU
300
and local peripheral components
302
are connected
CML Versatel Inc.
Kondracki Edward J.
Lefkowitz Sumati
Miles & Stockbridge P.C.
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