Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-04-02
2004-01-20
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S014000
Reexamination Certificate
active
06680213
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture, and more particularly to a wafer level method and system for fabricating contacts on semiconductor components.
BACKGROUND OF THE INVENTION
Semiconductor components such as dice, packages, and interconnects, are typically fabricated on a single substrate (e.g., a wafer or a panel) using wafer level fabrication processes. One step that is often performed at the wafer level is the fabrication of contacts on the components. For example, solder bumps can be fabricated on semiconductor dice using a deposition process, permitting controlled collapse chip connections (C4) to be made for packaging. As another example, solder balls can be fabricated on semiconductor packages by bonding pre-formed balls using solder reflow performed with a furnace or a laser. Often the solder balls are arranged in a ball grid array (BGA), or a fine ball grid array (FBGA), and function as the terminal contacts for the packages.
One aspect of wafer level fabrication processes is that the components on the substrate can have different characteristics making some components “good” and some components “defective” or “substandard”. For example, physical defects can occur in some of the components on the substrate making these components non-functional. Other components on the substrate can be functional, yet have substandard electrical characteristics. One important electrical characteristic is the speed with which the components process signals. Some functional components can have speed characteristics that make the components unsuitable for a particular application.
In the past it has been conventional to form contacts on all of the components contained on a substrate, regardless of the characteristics of the components. For example, conventional C4 deposition processes bump all of the dice contained on a wafer. Similarly, conventional solder reflow processes bond solder balls to all of the components on a panel. In both cases, contacts are formed on the defective and substandard components as well on the good components. One shortcoming of these conventional contact fabrication processes is that time and materials are wasted in forming the contacts on the defective and substandard components.
The present invention recognizes that it is advantageous for a contact fabrication process to consider the characteristics of the components prior to forming the contacts on the components. Accordingly, the present invention utilizes testing in combination with contact fabrication to improve wafer level fabrication processes for semiconductor components.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for fabricating contacts on semiconductor components is provided. Also provided are a system for performing the method, and improved semiconductor components fabricated using the method.
Initially, a substrate containing multiple semiconductor components is provided. The substrate can comprise a semiconductor wafer, or a portion thereof, containing multiple semiconductor dice or semiconductor packages. Alternately, the substrate can comprise a panel made of an organic material, such as a glass filled resin, containing multiple semiconductor packages. Each component includes a pattern of component contacts, such as bond pads, in electrical communication with integrated circuits contained on the component.
As a first step, the components on the substrate are tested to evaluate and characterize the components. The testing step can include “functional” tests for evaluating a gross functionality of the components, as well as “parametric” tests for evaluating various electrical characteristics of the components (e.g., speed). In addition to evaluating the components, the testing step “maps” the substrate by characterizing each component, and identifying its unique location on the substrate.
Test data from the testing step is then used to fabricate contacts on only those components that meet a predetermined criteria. This saves time and materials as contacts are not formed on the components that do not meet the predetermined criteria. Representative predetermined criteria include functionality, speed and reparability.
In a first embodiment of the invention, the components comprise semiconductor dice contained on a wafer, and the contacts comprise contact bumps formed on die bond pads using a ball bumper apparatus. The ball bumper apparatus uses preformed solder balls that are reflow bonded to the bond pads using a laser. In addition, the ball bumper apparatus is programmed with the test data to bump only those dice that meet the predetermined criteria. A system for performing the first embodiment method includes the ball bumper apparatus, and a wafer prober for testing the dice. The wafer prober includes a probe card having probe contacts in electrical communication with test circuitry.
In a second embodiment of the invention, the components comprise semiconductor packages contained on a panel, and the contacts comprise contact bumps formed on bump bonding pads using a ball bumper apparatus. A system for performing the second embodiment method includes the ball bumper apparatus, and a test socket for testing the packages, The test socket includes spring loaded electrical connections (e.g., “POGO PINS”) in electrical communication with test circuitry, which are configured to electrically engage the bump bonding pads. This test method provides a process advantage in that the bump bonding pads are typically plated with a non-oxidizing metal (e.g., gold) such that low resistance electrical connections can be made for testing.
In a third embodiment of the invention, the components comprise semiconductor dice contained on a wafer. The contacts comprise contact bumps formed on the die bond pads using a stenciling process. For performing the stenciling process, a stencil mask is formed on the wafer by depositing a polymer layer which is patterned with openings using a laser scanner programmed with test data from the testing step. Using the stencil mask, a conductive material, such as solder or a conductive polymer in viscous form, is squeegeed into the openings, and then heated to bond the material to the bond pads. The stencil mask is then stripped leaving the contact bumps. A system for performing the third embodiment includes a wafer prober for testing the dice, a laser scanner for patterning the polymer layer, and a furnace for heating the squeegeed conductive material.
In a fourth embodiment of the invention, the components comprise semiconductor dice contained on a wafer. The contacts comprise contact bumps formed by bonding pre-formed solder balls to the die bond pads using a reflow process. For performing the reflow process a ball alignment tool includes a polymer film which is patterned with openings using a laser scanner programmed with test data from the testing step. The openings in the polymer film are in flow communication with a vacuum and function to hold the solder balls on the die bond pads during reflow bonding in a furnace. A system for performing the fourth embodiment includes a wafer prober for testing the dice, a laser scanner for patterning the polymer film, the ball alignment tool for aligning and retaining the solder balls on the component contacts, and a furnace for reflowing the solder balls.
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Farnworth Warren M.
Kelly Douglas
Wood Alan G.
Berezny Nema
Gratton Stephen A.
Jr. Carl Whitehead
Micro)n Technology, Inc.
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