Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-12
2004-10-05
Wille, Douglas (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S268000, C438S270000
Reexamination Certificate
active
06800898
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an integrated circuit configuration comprising a conductive structure, which is buried in a substrate and is electrically connected to a region of the substrate, and also to a method for fabricating it.
U.S. Pat. Nos. 5,937,296 and 6,200,851 (see European patent publication EP 0 852 396 A2) describe an integrated circuit configuration, i.e. a circuit configuration which is arranged in a substrate, which is configured as a DRAM cell configuration. A memory cell of the DRAM cell configuration comprises a storage capacitor and a transistor. A storage node of the storage capacitor is buried in the substrate and adjoins a source/drain region of the transistor, which is configured as a doped region of the substrate. For each memory cell, a depression is produced in the substrate. A bottom and sidewalls of a lower part of the depression are provided with a capacitor dielectric. The lower part of the depression is filled with doped polysilicon, thereby producing the storage node. Afterward, further doped polysilicon is introduced into the depression, the polysilicon directly adjoining the substrate on a sidewall of the depression. As a result of a heat treatment step, dopant of the polysilicon diffuses into the substrate, where it forms the source/drain region of the transistor. After the production of a gate dielectric, a gate electrode is produced above the storage node in the depression. A further source/drain region of the transistor is produced above the source/drain region, with the result that the transistor is a vertical transistor wherein a channel current runs perpendicularly with respect to a surface of the substrate.
U.S. Pat. No. 5,497,017 describes an integrated circuit configuration which is a DRAM cell configuration. A memory cell of the DRAM cell configuration comprises a storage capacitor and a transistor. A bit line is buried in a substrate and electrically connected to a source/drain region of the transistor. In order to produce the bit line, a trench is produced in the substrate, the sidewalls and bottom of which trench are provided with an insulating structure. The trench is filled with tungsten, the bit line thereby being produced. Afterward, a part of the substrate and of the insulating structure is removed on an upper part of a sidewall of the trench, with the result that the bit line is laterally uncovered. The source/drain region of the transistor is subsequently produced by means of selective epitaxy. By means of further selective epitaxy, a channel region arranged above the source/drain region and a further source/drain region arranged above the channel region are produced. The transistor is configured as a vertical transistor.
K. Nakajima “Formation mechanism of ultrathin WSiN barrier layer in a W/WN
x
/Si system”, Applied Surface Science 117/118 (1997), 312, describes a gate electrode having a high electrical conductivity. A lower part of the gate electrode, which adjoins a gate dielectric, is composed of doped polysilicon. An upper part of the gate electrode is composed of tungsten. A diffusion barrier containing nitrogen is arranged between the upper part and the lower part of the gate electrode. The diffusion barrier comprises a layer containing the elements Si, N and W. The diffusion barrier prevents the tungsten from being siliconized in particular at higher temperatures, which would lead to a lower electrical conductivity of the gate electrode. In order to produce the diffusion barrier, a tungsten target is sputtered in a gas mixture comprising Ar and N
2
.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit configuration comprising a conductive structure which is buried in a substrate and is electrically connected to a region of the substrate, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which can be fabricated with low process complexity and in the case of which, at the same time, the conductive structure can have a high electrical conductivity. It is a further object of the invention to specify a method for fabricating such an integrated circuit configuration and a method of producing a DRAM structure with buried bit lines or trench capacitors.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit configuration, comprising:
a substrate having a depression formed therein with a bottom, sidewalls, a lower part, and a higher part;
an insulating structure formed on the bottom and sidewalls of the lower part of the depression;
a conductive structure having a first part with a first electrical conductivity disposed in the lower part of the depression, and a second part having a second electrical conductivity, lower than the first electrical conductivity, disposed in the higher part of the depression and adjoining a region of the substrate at a portion of at least one of the sidewalls of the depression; and
a diffusion barrier arranged between the first part and the second part of the conductive structure.
In other words, the problems associated with the above state of the art are solved with the novel integrated circuit configuration that comprises a conductive structure, which is buried in a substrate and is electrically connected to a region of the substrate, wherein the conductive structure comprises a first part, a second part and a diffusion barrier. The substrate has a depression. A bottom and sidewalls of a lower part of the depression are provided with an insulating structure. The first part of the conductive structure, which has a first electrical conductivity, is arranged in the lower part of the depression. The second part of the conductive structure, which has a second electrical conductivity, which is lower than the first electrical conductivity, is arranged in a higher part of the depression and adjoins the region of the substrate at a part of at least one of the sidewalls of the depression. The diffusion barrier is arranged between the first part and the second part of the conductive structure.
In accordance with an added feature of the invention, the first part of the conductive structure contains a metal (preferably tungsten); the second part of the conductive structure contains polysilicon; and the diffusion barrier contains nitrogen (preferably tungsten, silicon, and nitrogen).
In accordance with an additional feature of the invention, the substrate contains silicon; the polysilicon of the second part of the conductive structure is doped polysilicon; and the substrate is doped in the region of the substrate adjoined by the second part of the conductive structure.
In accordance with another feature of the invention, the integrated circuit configuration is configured as a DRAM cell configuration with memory cells each having at least one transistor. In one embodiment, the conductive structure forms a bit line; and the region of the substrate adjoined by the second part of the conductive structure is a source/drain region of the transistor.
In accordance with again a further feature of the invention, an insulation covers the conductive structure and portions of the sidewalls of the depression above the conductive structure; a gate electrode of the transistor is disposed in the depression and isolated from the conductive structure and the substrate by the insulation; and a further source/drain region of the transistor is disposed above the source/drain region and adjoins the sidewall of the depression.
In accordance with again an alternative embodiment of the invention, the integrated circuit configuration is configured as a DRAM cell configuration with memory cells each having at least one transistor and a capacitor. In that case, the conductive structure forms a storage node of the capacitor; the insulating structure is configured to act as a capacitor dielectric of the capacitor; and the region of the substrate adjoined by the second part of the conductive structure is a
Cappelani Annalisa
Sell Bernhard
Willer Josef
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
Wille Douglas
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