Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-04-22
2004-03-16
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100, C365S189090
Reexamination Certificate
active
06707727
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal transmission technique. More particularly, a first aspect of the present invention relates to a driver circuit used for transmitting signals between LSI chips or between elements or circuit blocks in an LSI chip, and a second aspect of the present invention relates to a receiver circuit and signal transmission system capable of transmitting signals at high speed. Further, a third aspect of the present invention relates to a timing signal generator circuit of a wide range of operation frequencies, and a fourth aspect of the present invention relates to a signal transmission technique involving the driver circuit, receiver circuit, and signal transmission system, capable of transmitting signals at high speed.
2. Description of the Related Art
Recently, the performance of information processing equipment such as computers has improved greatly. In particular, an improvement in the performance of DRAMs (dynamic random access memories) and processors is drastic. To keep pace with such improvement, signal transmission speeds must be increased.
For example, a speed gap between a DRAM and a processor in a computer hinders the performance of the computer. As the size of each chip increases, not only signal transmission between chips but also signal transmission between elements or circuit blocks in each chip becomes critical to the performance of the chip. Also critical is signal transmission between devices that form a multiprocessor server or between a server and peripheral circuits. To realize high-speed signal transmission, it is required to provide a driver circuit capable of transmitting signals at high speed.
High-speed signal transmission is needed not only between discrete units such as between a server and a main storage device, between servers connected to each other through a network and between printed boards but also between chips and between elements or circuit blocks in a chip due to an improvement in integration of LSIs and a decrease in power source voltage and signal amplitude. To improve the transmission speed, it is necessary to provide a receiver circuit and signal transmission system capable of correctly transmitting and receiving signals at high speed.
The receiver circuit must operate at a correct timing to receive signals transmitted at high speed between LSIs. To realize the correct reception timing, it is necessary to generate a correct timing signal. For this purpose, there are a DLL (delay locked loop) technique and a PLL (phase locked loop) technique. If a cable connecting a server to a main storage device is long or has poor transmission characteristics, an operation frequency must be dropped to correctly transmit signals through the cable. This requires a timing signal generator capable of generating a correct timing signal at high speed and operating in a wide frequency range. It also requires a signal transmission technique capable of preventing waveform disturbance due to high-frequency signal components and line-to-line interference.
Prior arts and the problems thereof will be explained later, and in detail, with reference to drawings.
SUMMARY OF THE INVENTION
An object of a first aspect of the present invention is to provide a driver circuit capable of correctly transmitting signals without waveform distortion or inter-code interference.
An object of a second aspect of the present invention is to provide a receiver circuit and a signal transmission system capable of correctly transmitting and receiving signals at high speed.
An object of a third aspect of the present invention is to provide a timing signal generator circuit having a simple structure capable of operating in a wide frequency range to generate a correct, high-speed timing signal without jitter.
An object of a fourth aspect of the present invention is to provide a signal transmission technique capable of correctly transmitting signals at high speed without waveform distortion due to high-frequency signal components or line-to-line interference.
According to a first aspect of the present invention, there is provided a driver circuit for transmitting signals, comprising an output driver; a front driver for driving the output driver; and a level adjuster for adjusting the output level of the front driver, so that the output driver outputs a signal having a specific level varied in response to an output level of the front driver.
The output driver may include a drain-grounded push-pull structure employing p-channel and n-channel MOS transistors. The output driver may be a voltage amplifier circuit whose output level is varied by adjusting an output voltage level of the front driver. The output driver may be a current-voltage converter circuit whose output voltage level is varied by adjusting an output current level of the front driver. The output driver may include a feedback circuit for dropping output impedance.
The front driver may include a variable gain unit cooperating with the level adjuster, to adjust a level of an input signal level; and an amplifier for amplifying the level-adjusted input signal. The front driver may be a current limiting inverter for receiving an input signal, an output level of the current limiting inverter being adjusted by controlling a current passing thereto by the level adjuster. An output of the output driver may be changed in response to a sequence of past digital values, to equalize characteristics of a transmission line.
The front driver may comprise a plurality of drivers that are commonly connected to the output driver, the drivers of the front driver receiving data generated from a sequence of past digital data provided by the output driver and equalizing characteristics of a transmission line. The drivers of the front driver may have respective coefficients, multiply received data by the coefficients, and supply the products to the output driver.
The front driver may comprise first and second drivers, a digital input signal to the driver circuit being directly supplied to the first driver of the front driver, and at the same time, being delayed by a bit time, inverted, and supplied to the second driver of the front driver, thereby equalizing characteristics of a transmission line. The first and second drivers of the front driver may be arranged in parallel with each other; the second driver of the front driver may multiply the delayed and inverted signal by a coefficient; and the outputs of the first and second drivers of the front driver may be added to each other to drive the output driver. The characteristics of the transmission line may be equalized by compensating for attenuation in high-frequency components in signals that are provided by the output driver and are transmitted through the transmission line. The front driver may comprise a plurality of driver pairs, the driver pairs of the front driver being interleaved to carry out parallel-to-serial conversion.
The output driver may include a source-grounded push-pull structure employing p-channel and n-channel MOS transistors. A gate voltage of the p-channel MOS transistor of the output driver may be set above an intermediate voltage, which is between a high source voltage and a low source voltage, and a gate voltage of the n-channel MOS transistor of the output driver may be set below the intermediate voltage when the output driver provides the intermediate voltage. The gate of the n-channel MOS transistor may be driven by a drain-grounded n-channel MOS circuit and the gate of the p-channel MOS transistor may be driven by a drain-grounded p-channel MOS circuit.
The output driver may be driven by a voltage that is lower than the high source voltage by a predetermined value and a voltage that is higher than the low source voltage by a predetermined value. The output driver may include a replica driver that equalizes an intermediate voltage between voltages for driving the output driver to an intermediate voltage between the high source voltage and the low source voltage.
According to a second aspec
Cheung Tsz-Shing
Gotoh Kohtaroh
Takauchi Hideki
Tamura Hirotaka
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Le Thong
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