Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-04-15
2004-09-28
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06798702
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically to a semiconductor memory device having a data line redundancy replacement circuit of a shifting type.
2. Description of the Background Art
A semiconductor memory device has redundancy memory cells in addition to normal memory cells. Yield is enhanced by replacing and repairing defective memory cell among normal memory cells with a redundancy memory cell.
Recently, there has been a strong demand to increase bus width in order to improve data transfer rate. Accordingly, the number of data lines tends to be larger, correspondingly making the number of column address smaller. Particularly in a dynamic random access memory (DRAM) embedded along with a logic circuit on a semiconductor device to implement system-on-chip, a configuration has been changing from one with 32-bit bus width and 256-bit column address (adopted in a conventional memory) to, for example, one with 256-bit bus width and 16-bit column address.
Conventionally, a defective chip has been repaired through replacement of a bit line by making a switch of a column address. When the number of columns is small, however, high repair ratio cannot be expected without preparing a relatively large number of redundancy memory cells. Therefore, in many cases, a redundancy memory cell and a redundancy data line connected thereto are prepared so as to replace a data line connected to a defective memory cell or a data line having a defect (hereinafter, referred to as a defective data line) with a redundancy data line.
FIG. 13
is a block diagram showing a conventional example of a semiconductor memory device with a data line redundancy replacement configuration.
Referring to
FIG. 13
, a conventional semiconductor memory device includes: a memory cell array
502
; a row decoder
504
selecting a row in memory cell array
502
; a read amplifier and write driver circuit
506
reading and writing data from/to memory cell array
502
through a data line; a fuse circuit
508
programming replacement information according to a position of a defective data line; a shift information latch circuit
510
outputting shift control signal SFT<n:0> upon receiving an output from fuse circuit
508
; a data line shift circuit
512
determining a data line pair to be used from n+1 normal data line pairs and a redundancy data line pair according to shift control signal SFT<n:0>; and an input/output circuit
514
communicating data with the data line pair selected by data line shift circuit
512
.
N+1 normal data line pairs and a redundancy data line pair read and write data from/to memory cell array
502
. Read amplifier and write driver circuit
506
includes a plurality of read amplifier and write driver units
516
.
Input/output circuit
514
includes a plurality of input/output buffers
518
corresponding to data signals DQ<0>-DQ<n> respectively. Data line shift circuit
512
includes shift switches
512
.
0
-
512
.
n
corresponding to the plurality of input/output buffers
518
respectively.
The normal data line pair includes data lines IO, NIO. The redundancy data line pair includes data lines SIO, NSIO.
The data line pair IO, NIO is connected to a memory cell through a sense amplifier circuit and a bit line in memory cell array
502
. A read amplifier contained in read amplifier and write driver unit
516
amplifies data of the data line pair to generate a signal DBRA<n+1:0>. A write buffer circuit contained in read amplifier and write driver unit
516
drives the data line pair upon receiving a write data signal provided by signal DBWA<n+1:0>.
If a defect is found in a data line in the memory cell array, those shift switches
512
.
0
-
512
.
n
which correspond to the defective data line are switched so that data in a next adjacent data line can be used. By shifting all the data lines positioned higher in bits than the defective data line, a redundancy data line can be used in place of the defective data line.
FIG. 14
is a circuit diagram showing a configuration of ith shift switch
512
.
i
in FIG.
13
.
Referring to
FIG. 14
, shift switch
512
.
i
includes: an inverter
538
receiving and inverting shift control signal SFT<i>; a transmission gate circuit
544
activated in accordance with an output of inverter
538
and transmitting signal DBWB<i> as signal DBWA<i>; and a transmission gate circuit
546
activated in accordance with shift control signal SFT<i> and transmitting signal DBWB<i> as signal DBWA<i+1>. Transmission gate circuit
544
is activated when shift control signal SFT<i> is “0”, while transmission gate circuit
546
is activated when shift control signal SFT<i>is “1”.
Shift switch
512
.
i
further includes a transmission gate circuit
540
activated in accordance with an output of inverter
538
and transmitting signal DBRA<i> as signal DBRB<i>; and a transmission gate circuit
542
activated in accordance with shift control signal SFT<i> and transmitting signal DBRA<i+1> as signal DBRB<i>. Transmission gate circuit
540
is activated when shift control signal SFT<i> is “0”, while transmission gate circuit
542
is activated when shift control signal SFT<i> is “1”.
When shift control signal SFT<i> in
FIG. 14
is “0”, “no shift” is indicated and signals DBWA<i>, DBRA<i> are selected. On the other hand, when shift control signal SFT<i> is “1”, “shift” is indicated and signals DBWA<i+1>, DBRA<i+1> are selected.
FIG. 15
is a circuit diagram showing a configuration of transmission gate circuit
544
in FIG.
14
.
Referring to
FIG. 15
, transmission gate circuit
544
includes: an inverter
552
receiving and inverting a signal provided to node E; a P channel MOS transistor connected between nodes A and B and receiving an output of inverter
552
at a gate; and an N channel MOS transistor
556
connected between nodes A and B and having a gate connected to node E. Transmission gate circuit
544
connects node A and node B when node E is supplied with H level, while it disconnects node A from node B when node E is supplied with L level.
Transmission gate circuits
546
,
540
,
542
are of the same configuration as transmission gate circuit
544
, and description thereof will not be repeated.
FIG. 16
shows relation between a defective data line and shift control signal SFT<n:0> in FIG.
13
.
Referring to
FIGS. 13 and 16
, when shift control signal is “0” or “1”, “no shift” or “shift” is indicated respectively.
At initial setting, fuse circuit
508
has not been programmed and shift control signals SFT<
0
>-SFT<n> are all “0”. Connection status of shift switches
512
.
0
-
512
.
n
in
FIG. 13
at that time is shown. At initial setting, redundancy data line pair is not used.
For example if a defect FA is present in n−1th data line pair of 0−nth data line pairs, fuse circuit
508
will be programmed in such a way that shift control signals SFT<0>-SFT<n−2> are set to be “0” and shift control signals SFT<n−1>, SFT<n> are set to be “1”.
Then, at initial state as shown in
FIG. 13
, connection of two shift switches (shift switches
512
.
n−
1,
512
.
n
) among shift switches
512
.
0
-
512
.
n
connected to 0−nth normal data line pairs is changed. Consequently, input/output buffer
518
inputting/outputting signal DQ<n> is connected to a redundancy data line pair and an input/output buffer inputting/outputting signal DQ<n−1> is connected to nth normal data line pair. N−1th data line pair having a defect FA is not connected to any input/output buffer
518
.
In above-described configuration of a semiconductor memory device, if a defect is found in the inside of memory cell array
502
as defect FA, a defective chip can be repaired by means of data line shift circuit
512
. If a defect is fou
Nelms David
Nguyen Thinh T
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