Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-09
2004-09-07
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S013000, C703S014000, C703S015000
Reexamination Certificate
active
06789237
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the design of microelectronic circuits and systems, and more particularly, to simulators for evaluating the performance of microelectronic circuits and systems prior to fabrication.
BACKGROUND OF THE INVENTION
In the process of designing circuits, particularly large scale integrated circuits, it is normal practice to mathematically model the electrical circuits. Many circuit simulators have been developed to mathematically model the circuits. Particularly, the outputs of the circuit are modeled as a function of the inputs to the circuit. The mathematical model is used to determine various response characteristics of the circuit.
Circuit simulation has long been an essential step in the design and manufacture of microelectronic circuits and systems. Circuit simulators are typically software based and are designed to accept a description of the circuit that defines the circuit topology and element values. Simulators typically simulate circuits which contain linear devices such as resistors capacitors and inductors, voltage and current sources and nonlinear devices such as diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET) and metal oxide semiconductor field effect transistors (MOSFET). The simulator can typically be configured to perform DC analysis, AC small signal analysis and transient analysis.
The modeling of the larger overall circuit can be extremely complex in large scale integrated (LSI) circuits, very large scale integrated (VLSI) circuits, and ultra large scale integrated (ULSI) circuits. Simulation of extremely LSI, VLSI, and ULSI circuits require better simulators. As the size and complexity of circuits has grown, so has the need for simulators that are capable of testing larger and more complex circuits.
A traditional simulation tool, such as a dynamic simulator (SPICE, for example), can be used. However, because of the large number of circuit elements involved, a complete simulation becomes extremely time consuming and may exceed the storage capability of the processing system on which the simulation is run. Dynamic simulators such as SPICE-like simulators that are based on integration of nonlinear ordinary differential equations are useful in analyzing nonlinear circuit but are relatively inefficient for highly interconnected circuits or networks.
In recent years, moment matching techniques, e.g., [
1
]-[
3
], havegrown to be among the most popular linear circuit simulation techniques. The moments of a transfer function of order n results from expanding the transfer function into a Taylor series around s=0 as given by
H
(
s
)
=
1
+
a
1
s
+
a
2
s
2
+
…
+
a
m
s
m
1
+
b
1
s
+
b
2
s
2
+
…
+
b
n
s
n
=
1
+
m
1
s
+
m
2
s
2
+
m
3
s
3
+
…
,
(
1
)
The i
th
moment of the transfer function m
1
is the coefficient of s
1
in the series expansion. To illustrate the relation between the moments, poles, and residues of the transfer function, (1) can be expressed as a partial fractions sum given by
H
(
s
)
=
k
1
s
-
p
1
+
k
2
s
-
p
2
+
…
+
k
n
s
-
p
n
,
(
2
)
where p
1
is the i
th
pole of the transfer function and k
1
is the corresponding residue. By expanding each term in equation (2) into powers of s, the moments of H(s) can be expressed as
m
0
=
-
(
k
1
p
1
+
k
2
p
2
+
…
+
k
n
p
n
)
,
m
1
=
-
(
k
1
p
1
2
+
k
2
p
2
2
+
…
+
k
n
p
n
2
)
,
⋮
m
2
n
-
1
=
-
(
k
1
p
1
2
n
+
k
2
p
2
2
n
+
…
+
k
n
p
n
2
n
)
.
(
3
)
This favorable reciprocal relation between the moments and the poles stresses the dominant poles with smaller magnitudes. Dominant poles are of most interest when evaluating the transient response. This characteristic makes the moments very popular in circuit simulation. Moreover, the moments around s=0 can be calculated very easily for tree structured and tree like interconnect in linear time with the number of elements in the circuit [
1
]-[
5
]. Path tracking techniques for efficiently calculating the moments for tree and tree like structures where introduced in [
4
] and [
5
]. Note that tree like structures include capacitively and inductively coupled trees. Also, other techniques have been developed in [
5
] to extend the efficiency of path tracking techniques to circuits with few resistive and inductive loops. The overwhelming majority of interconnects in integrated circuits fall into these categories of circuits. The efficiency of calculating the moments around s=0 further increased the popularity of moment matching techniques.
Numerous moment matching techniques are known in the art for large linear circuit analysis. One technique in particular is the asymptotic Waveform Evaluation (AWE) algorithm. The AWE technique [
2
], [
3
] employs moment matching by calculating the first 2q moments of the transfer function around s=0 to determine the first q dominant poles and corresponding residues of the transfer function. The moments at node j are approximated by
m
0
j
=
-
(
k
1
j
p
1
+
k
2
j
p
2
+
…
+
k
4
j
p
q
)
,
m
1
j
=
-
(
k
1
j
p
1
2
+
k
2
j
p
2
2
+
…
+
k
q
j
p
q
2
)
,
⋮
m
2
q
-
1
j
=
-
(
k
1
j
p
1
2
q
+
k
2
j
p
2
2
q
+
…
+
k
q
j
p
q
2
q
)
.
(
4
)
where the terms representing poles with magnitude larger than p
q
are neglected and p
1
<p
2
< . . . <p
q
. Hence, the first q most dominant poles and corresponding residues can be calculated by solving the set of 2q nonlinear equations with 2q variables in equation (4). Indirect methods to solve equation (4) were also developed in [
2
].
The process by which the moments are determined does not allow calculating the moments at few selected nodes of a circuit and the moments have to be calculated at all nodes since the i+1 moment at any node j depends on the i
th
moments at all the nodes [
1
]-[
5
]. However, the AWE techniques only uses the moments at a single node at a time to calculate the response at that node and all the moments calculated at other nodes are not used. Hence, techniques of the prior art such as the AWE techniques are referred to as Single-point Moment Matching (SMM) techniques. These techniques improve the approximation accuracy by calculating more moments at each node.
As will be shown, accuracy can be also improved by using the information in the moments at different nodes simultaneously. However, multiple input circuits are becoming increasingly cammon in integrated circuits with the increasing importance a analyzing interconnects with capacitive and inductive coupling. Also, important structures such as the power distribution networks are typically multi-input circuits. A major problem with SMM techniques is the inherent numerical instability with higher order approximations. The set of equations (4) is very sensitive to numerical errors with high q due to the high powers of the poles involved. Even with a moderate disparity in the pole values, higher moments very quickly contain no information about larger magnitude poles due to truncation errors. For that reason SMM techniques are limited to less than eight to ten poles [
4
]-[
6
]. With complicated integrated circuits, increasing inductance effects, higher inductive and capacitive coupling, and higher operating frequencies, approximations with orders higher than can be achieved by single-point moment matching become necessary. The poles of a circuit effectively represent its harmonics. The more complex the harmonics, the greater the number of poles required for accurate simulation. For simple RC (resistive-capacitance) circuits, usually only a few dominant poles are required for high accuracy simulation. Under such conditions, the AWE approximation method is quite accurate and is widely used for simple RC circuits. But, for today's more complex RLC circuits (resistive-inductive-capacit
Northwestern University
Reinhart Boerner Van Deuren s.c.
Siek Vuthe
LandOfFree
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