Configurable buffer for multipass applications

Details Configurable buffer for multipass applications Configurable buffer for multipass applications

2001-05-14

2004-03-02

Tung, Kee M. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Graphic display memory controller

C345S537000, C345S582000

Reexamination Certificate

active

06700583

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Reservation of Copyright
The disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document, or the patent disclosure as it appears in the U.S. Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
2. Field of the Invention
This invention relates to video graphics processing.
3. Background of the Invention
Graphics rendering is an important part of many representational and interactive applications for computers. In three-dimensional (or ‘3D’) graphics rendering, an image of a 3D rendering space is presented on a display frame as if the space is being viewed through a two-dimensional display plane. As shown in
FIG. 1
, the display frame
10
is an array of individual picture elements (or ‘pixels’)
20
. Each pixel represents a sample of the display plane at a specified location and has a color value that corresponds to the color of the rendering space as viewed through the display plane at that location. The pixels are closely spaced, and the viewer's visual system performs a filtering of the individual pixels to form a composite image. If an image is properly partitioned into pixels that are sufficiently close together, the viewer perceives the displayed array as a virtually continuous image.
Three-dimensional ‘wire frame’ models of objects in the rendering space are constructed using graphics primitives (e.g. triangles or other polygons). Each primitive is defined by a set of vertices that have values indicating location (e.g. in an XYZ coordinate space) and quality (e.g. color). Each of these vertex values may also have subvalues; for example, a vertex color value may include a subvalue for each of the components in the colorspace (e.g. RGB, HSV, YCbCr), a subvalue for luminance, and/or an opacity or ‘alpha’ subvalue.
Some or all of the rendering of the object models into pixels may be performed in software. Alternatively, the sets of vertices may be presented to rendering hardware, either directly by the software application or via an application programming interface (API) such as the Direct3D component of the DirectX API suite (Microsoft Corp, Redmond, Wash.) or the OpenGL API (Silicon Graphics, Inc., Mountain View, Calif.).
One example of rendering hardware suitable for receiving sets of vertices is a 3D graphics architecture as shown in FIG.
2
. Raster engine
120
scan-converts (or ‘rasterizes’) polygons into data sets called ‘fragments’ that correspond to pixels in the display frame and have values relating to such qualities as color (e.g. R, G, B, and alpha), depth (i.e. Z location) and texture. Fragments may be processed in a pipeline
130
(also called a ‘pixel pipeline’) before their color values are incorporated into corresponding pixels of a frame buffer
140
that represents the display frame. As shown in
FIG. 3
, a graphics architecture may also include a transform and lighting engine
110
that performs coordinate transform operations (e.g. translation, rotation, scaling), lighting operations, and/or clipping operations on vertices before rasterization.
An object rendered using only a few polygons may have large flat surfaces and appear simplistic and artificial. While detail features may be added to a surface by tessellation (i.e. increasing the number of primitives used to model the surface), adding features in this manner may substantially increase the number of polygons in the image and reduce the fill rate to an unacceptable level.
A technique called ‘texture mapping’ is used to add realistic detail to the surface of a rendered object without modeling the features explicitly. This technique applies a texture map (i.e. an array of texture elements or ‘texels’ defined in an ST texture coordinate space) to the surface of a polygon to create the illusion of surface detail. Texture mapping may be performed in a 3D graphics architecture by assigning to each fragment (for example, in the raster engine or the transform and lighting engine) an ST coordinate pair (s, t) that indicates a particular texel in the texture map.
FIG. 4
shows a block diagram of a 3D graphics architecture capable of supporting texture mapping that includes a pipeline
132
having a texture lookup and filter engine (TL&F)
150
. As shown in
FIG. 5
, TL&F
150
references a texture map stored in storage
170
according to a coordinate pair received from raster engine
122
. TL&F
150
receives a texel value as indicated by the coordinate pair and forwards the texel value to a pixel combiner
160
. Raster engine
122
may output other quality values or subvalues for a fragment (e.g. a base color value) that are combined with the texel value in pixel combiner
160
to produce the color value of the pixel to be stored in frame buffer
140
. A pixel pipeline
132
may support multiple texture datapaths (e.g. multiple instances of TL&F
150
and/or multiple passes through one such unit), and pixel combiner
160
may receive values from more than one texture map (e.g. one or more lighting maps) for a single fragment.
SUMMARY
A configurable buffer according to one embodiment of the invention has first and second buffer storage areas, first and second input ports, and first and second output ports. The buffer is configured and arranged to receive first portions of a plurality of data sets through the first input port. The buffer is also configured and arranged to receive a buffer control signal. When the buffer control signal has one state, the buffer is configured and arranged to store some of the first portions in each of the two buffer storage areas. When the buffer control signal has a different state, the buffer is configured and arranged to store the first portions in the first buffer storage area, to receive second data values through the second input port, and to store the second data values in the second buffer storage area.


REFERENCES:
patent: 5977977 (1999-11-01), Kajiya et al.
patent: 6052126 (2000-04-01), Sakuraba et al.
patent: 6236405 (2001-05-01), Schilling et al.
patent: 6384824 (2002-05-01), Morgan et al.
patent: 2002/0140703 (2002-10-01), Baker et al.
patent: 2002/0184282 (2002-12-01), Yuval et al.

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