Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-28
2004-10-05
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C365S200000, C257S202000, C326S040000
Reexamination Certificate
active
06802043
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-096676, filed Mar. 29, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of macros. More specifically, the invention relates to a technique to maintain reliability of signals transmitted in a semiconductor integrated circuit.
2. Description of the Related Art
A system LSI having a plurality of functions integrated on one chip has become a focus of attention in accordance with recent improvement in semiconductor manufacturing technique.
FIG. 1A
is a schematic block diagram showing a configuration of a prior art system LSI. As shown in
FIG. 1A
, a system LSI
1
includes a plurality of macros A
1
to A
6
formed on a single semiconductor substrate. The “macro” means a collection of semiconductor elements and corresponds to a block that carries out a specific function by itself. More specifically, the system LSI includes macros such as an SRAM (static random access memory), a DRAM (dynamic random access memory), and a CPU (central processing unit). The macros A
1
to A
6
are connected to each other by connection wires and cooperate with each other, thereby fulfilling a function of the system LSI.
It is needless to say that a method of designing a macro may vary from macro to macro; however, one macro can be designed by a plurality of design methods. This case will be described with reference to FIG.
1
B.
FIG. 1B
is a block diagram showing an internal structure of the macro A
1
shown in FIG.
1
A.
The macro A
1
is a DRAM macro having a function related to the DRAM as illustrated in FIG.
1
B. The DRAM macro A
1
includes both a DRAM block DRAM_BLK and a test circuit block TEST_BLK. The DRAM block DRAM_BLK is an area including a circuit for carrying out a memory function of the DRAM. The test circuit block TEST_BLK is an area including a test circuit having a function that is unnecessary when a user uses the DRAM block DRAM_BLK but necessary when the DRAM block DRAM_BLK is tested during the manufacture of the DRAM macro A
1
.
The DRAM block DRAM_BLK is designed by a manual design method such as a bottom-up method. The test circuit block TEST_BLK in the same macro need not be designed particularly by the manual design method in terms of its circuit arrangement. The test circuit block TEST_BLK might therefore be designed by an automatic design method using, e.g., a standard cell. Using a standard cell, circuits can be synthesized on the RTL (register transfer level) and their layout can be designed by automatic layout wiring. Consequently, a time period for design can be shortened more than when the DRAM macro A
1
is designed only by the bottom-up method.
An internal clock might be required when the test circuit conducts a test on the DRAM block DRAM_BLK. The test circuit block TEST_BLK therefore usually includes a clock generator. Since the clock generator is provided in the test circuit block TEST_BLK, it is designed by the automatic design method, too. However, a delay element is not generally included in a standard cell that is used as a library while automatic layout wiring is being performed by software. Delay time required for generating an internal clock is achieved by an inverter delay supplied by a plurality of inverters
2
connected in series, as shown in FIG.
1
C. Thus, a great number of inverters
2
are required when the frequency of the internal clock is low, with the result that the area of the DRAM macro increases. If the inverters are used to cause a delay, delay time greatly varies with voltage and process variations and a clock becomes difficult to control exactly.
The macros A
1
to A
6
are connected to each other by connection wires. As illustrated in
FIG. 1A
, a buffer
3
is provided halfway through a connection wire to prevent the waveform of a signal transmitted through the connection wire from being dulled. In
FIG. 1A
, the macro A
1
of large size is provided between the macros A
2
and A
6
. A connection wire for connecting the macros A
2
and A
6
has to take a long detour through the macro A
1
. Consequently, a long delay is caused in a signal when the signal is transmitted through the connection wire, thereby decreasing the operation reliability of the system LSI. Since the connection wire has to take a long detour, the layout of macros becomes difficult to design in a system LSI having a number of connection wires. From this viewpoint, the connection wire that connects macros A
2
and A
6
may pass over the macro A
1
. This layout is shown in FIG.
2
A. In this case, however, it is hard to insert a signal waveform-shaping buffer in a halfway portion of the connection wire. This is because the macro A
1
is not formed even taking into consideration a connection wire that is to pass over the macro A
1
itself. The waveform of a signal cannot be prevented from being dulled when the signal passes over the macro A
1
.
In order to arrange a connection wire over the macro A
1
, an area in which a metal wire necessary for forming the macro A
1
is formed, needs to be predetermined as a wiring inhibit area, as shown in
FIG. 2B. A
connection wire passing over the macro (macro passing wire) needs to be laid out in a space area other than the wiring inhibit area. While the wiring density in the wiring inhibit area is very high, it becomes low in the other areas because the macro passing wire simply passes over the area. In other words, the wiring density may vary in the same macro. A problem therefore occurs in the process of manufacturing a metal wiring layer. It is likely that the process precision in a low-density wiring area deteriorates if the process is optimized in accordance with a high-density wiring area and the process precision in a high-density wiring area deteriorates if the process is optimized in accordance with a low-density wiring area.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device according to an aspect of the present invention comprises:
a first semiconductor circuit having a first function;
a second semiconductor circuit having a second function different from the first function; and
a third semiconductor circuit provided in the second semiconductor circuit and having part of the first function, the third semiconductor circuit transmitting/receiving no signals to/from the second semiconductor circuit and operating independently of the second semiconductor circuit.
A method for designing a semiconductor device according to an aspect of the present invention comprises:
determining a first semiconductor circuit necessary for composing a first semiconductor circuit group which fulfils a first function and a plurality of second semiconductor circuits necessary for composing a second semiconductor circuit group which fulfils a second function;
selecting a second semiconductor circuit, which is to be designed by a same design method as that of the first semiconductor circuit group, from the second semiconductor circuit group; and
designing the first semiconductor circuit group including the selected second semiconductor circuit by a first design method and designing the second semiconductor circuit group excluding the selected second semiconductor circuit by a second design method, the second design method differing from the first design method, and the second semiconductor circuit in the first semiconductor circuit group transmitting/receiving no signals to/from the first semiconductor circuit and being independent of the first semiconductor circuit.
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patent: 6473352 (2002-10-01), Nishino et al.
patent: 6535999 (2003-03-01), Merritt et al.
patent: 6556490 (2003-04-01), Shubat et al.
patent: 6560740 (2003-05-01), Zuraski, Jr. et al.
patent: 2002/0097623 (2002-07-01), Suzuki et al.
patent:
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