Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2002-06-14

2004-01-13

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S101000, C327S530000

Reexamination Certificate

active

06677781

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device which includes a plurality of buffer circuits of signal pads operable in response to electric power supplied from a common power source line.
A packaged semiconductor integrated circuit device includes numerous terminals. Numerous bonding pads (each being referred to as ‘pad’ hereinafter) corresponding to respective terminals are formed on a chip.
FIG. 5
shows a buffer circuit
1
formed on the chip and interposed between a signal output pad
2
and an internal logic circuit constituted by logic circuits or the like. The buffer circuit
1
inverts an output signal of the internal logic circuit and outputs an inverted signal to the pad
2
. The buffer circuit
1
includes two MOS transistors
5
and
6
connected in series between power source lines
3
and
4
.
In the buffer circuit
1
shown in
FIG. 5
, the output signal of the internal logic circuit for example turns into L level from H level. In this moment, a feedthrough current Ia flows across the MOS transistors
5
and
6
from the positive power source line
3
to the negative power source line
4
. At the same time, a charge current Ib flows from the positive power source line
3
to an external circuit
7
via MOS transistor
5
and the pad
2
. Both the feedthrough current Ia and the charge current Ib flow through the positive power source line
3
. The positive power source line
3
has a resistance component. Hence, a significant voltage drop is caused in accordance with the currents Ia and Ib flowing through the positive power source line
3
. Such momentary voltage drop will develop into fluctuation in the voltage level of positive power source line
3
. Similar fluctuation will appear in the other power source line
4
because the negative power source line
4
has a resistance component, too.
The above-described voltage fluctuation (i.e., noise) caused in response to the switching of MOS transistors
5
and
6
becomes large with increasing frequency of an output signal of the internal logic circuit (i.e., the frequency of switching operations). The noise is transmitted to a power source pad (not shown) via the power source lines
3
and
4
. Then, the noise leaks out of the semiconductor integrated circuit device via a power source terminal connected to the power source pad. Furthermore, the noise is transmitted to other signal pad via other buffer circuit which is operable in response to electric power supplied from the power source line
3
. In this case, the noise leaks out of the semiconductor integrated circuit device via a signal terminal connected to this signal pad.
To reduce leakage of noises from the semiconductor integrated circuit, unexamined Japanese patent publication No. 11-177025 discloses a power supply line of internal logic circuits which is arranged in a zigzag pattern. According to this arrangement, the noise caused by the feedthrough current Ia is absorbed partly by a capacitance component of an internal logic circuit disposed at an intermediate portion of the zigzag power supply line and is suppressed by an inductance component of zigzag power supply line.
However, adopting the zigzag wiring pattern for the power supply line of internal logic circuits is disadvantageous in that the overall wiring distance increases excessively and accordingly a large voltage drop occurs in the long path of the power supply line. Namely, a voltage actually applied to each internal logic circuit is fairly smaller than the power source voltage applied to the power source pad. In other words, the internal logic circuit has a so small power voltage margin that the internal logic circuit may not operate properly when the voltage level of a power source fluctuates.
SUMMARY OF THE INVENTION
In view of the above-described problems, the present invention has an object to provide a semiconductor integrated circuit device which is capable of maintaining the power voltage margin of an internal logic circuit to an adequate level and is also capable of preventing the noises from leaking out of the semiconductor integrated circuit device when the noises are produced from buffer circuits of high-frequency signal pads provided for inputting and outputting signals having higher frequency components.
In order to accomplish the above and other related objects, the present invention provides a semiconductor integrated circuit device comprising at least one power source pad provided on a chip, a plurality of signal pads provided on the chip, at least one common power source line extending from the power source pad on the chip, buffer circuits provided for the signal pads, and power supply points of the common power source line for supplying electric power to the buffer circuits. The semiconductor integrated circuit device of the present invention is characterized in that the power supply points of the common power source line are classified into first power supply points for the buffer circuits of low-frequency signal pads and second power supply points for the buffer circuits of high-frequency signal pads. The low-frequency signal pads are used for inputting and outputting signals having relatively low frequency components, while the high-frequency signal pads are used for inputting and outputting signals having relatively high frequency components. And, a wiring distance from the power source pad to the second power supply points as well as a wiring distance from the first power supply points to the second power supply points are set to be relatively long in an overall wiring arrangement on the chip.
According to this arrangement, large noises generated in respective buffer circuits of the high-frequency signal pads greatly attenuate when the noises propagate via the long path of the common power source line to the low-frequency signal pads and to the power source pad. Hence, it becomes possible to prevent the noises from leaking out of the semiconductor integrated circuit device via respective low-frequency signal pads and also via the power source pad.
It is preferable that a group of the first power supply points and a group of the second power supply points are successively arranged on the common power source line extending from the power source pad. And, a wiring distance from the group of the first power supply points to the group of the second power supply points is longer than a wiring distance from the power source pad to the group of the first power supply points. The noises generated from the buffer circuits of the high-frequency signal pads surely attenuate during the propagation through the long path of the common power source line before they arrive at the low-frequency signal pads or to the power source pad.
Furthermore, it is preferable that a wiring distance from the power source pad to the first and second power supply points is determined considering high-frequency cutoff property of the common power source line which is dependent on a resistance component and a capacitance component of the common power source line. According to this arrangement, there is no necessity of extending respective power source lines so excessively. The chip size will not increase so much.
Furthermore, it is preferable that the resistance component and the capacitance component of the common power source line are taken into consideration at each wiring section between two adjacent first power supply points, each wiring section between two adjacent second power supply points, and a wiring section between the first power supply points and the second power supply points.
Furthermore, it is preferable that a capacitor is interposed between a positive common power source line and a negative common power source line. This is effective to suppress the noise having steep voltage changes caused by feedthrough current or charge/discharge current. As a result, the mutual distance between the power source pad and the power source supply points can be reduced. The chip size can be downsized.
For example, the low-frequency signal pads are

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