Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-01
2004-09-21
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000
Reexamination Certificate
active
06794712
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device providing planarly dispersed charge storing means (for example, charge traps in a nitride film in a MONOS type or MNOS type transistor, charge traps near the interface of a top insulating film and nitride film, small particle size conductors, and so forth) inside of a gate insulating film between a channel forming region and gate electrode of a memory transistor and basically operating to electrically inject charges (electrons or holes) into the charge storing means to store the same or to drain the same and to a process for production and write method for the same.
2. Description of the Related Art
As a nonvolatile semiconductor memory, a floating gate (FG) type nonvolatile semiconductor memory where charge storing means (floating gates) for holding charges are planarly dispersed, and a metal-oxide nitride-oxide semiconductor (MONOS) type nonvolatile semiconductor memory for example where the charge storing means are planarly dispersed are known.
In a MONOS type nonvolatile semiconductor memory, carrier traps in a nitride film (Si
x
N
y
(O<x<1, 0<y<1)) mainly responsible for holding charges or at a boundary (an interface) between a top oxide film and the nitride film spread out spatially dispersedly (that is, in the planar direction and thickness direction), so the charge retention characteristic is dependent on the energy and spatial distribution of the charges captured by the carrier traps in the Si
x
N
y
film.
When leakage current paths are locally generated in the tunnel insulating film, in the FG type nonvolatile semiconductor memory, a large number of the charges pass through the leakage current paths and the charge retention characteristic tends to decline, while in the MONOS type nonvolatile semiconductor memory, since the charge storing means are spatially dispersed, the local charges around the leakage current paths pass through the leakage current paths and only local leakage occurs so the charge retention characteristic of the storage element as a whole does not easily fall.
Therefore, in the MONOS type nonvolatile semiconductor memory, the problem of the reduction of the charge retention characteristic due to a reduction in the thickness of the tunnel insulating film is not as serious as that in the FG type nonvolatile semiconductor memory. Therefore, the scaling of a tunnel insulating film in a fine memory transistor with an extremely short gate length is better in the MONOS type nonvolatile semiconductor memory than the FG type nonvolatile semiconductor memory.
In a MONOS type nonvolatile semiconductor memory or other nonvolatile semiconductor memory with planarly dispersed charge storing means of the memory transistors, it is essential to realize a one-transistor type of call structure in order to reduce the cost per bit, increase the degree of integration, and realize a large-sized nonvolatile semiconductor memory.
In a MONOS type nonvolatile semiconductor memory or other nonvolatile semiconductor memory of the related art, however, the mainstream configuration has been for a two-transistor cell with a selected transistor connected to the memory transistor. At the present time, various studies are underway for establishment of single transistor cell technology.
In order to establish such single transistor cell technology, it is necessary to optimize the device structure, primarily the gate insulating film including the charge storing means, and improve the realiability and also to improve the disturbance characteristic. Further, as one measure for improving the disturbance characteristic of a MONOS type nonvolatile semiconductor memory, studies are being conducted on setting the tunnel insulating film thicker (1.6 nm to 2.0 nm).
Further, in order to reduce the cost per bit of a nonvolatile semiconductor memory and increase the integration density, it is necessary to miniaturize the memory cell and also reduce the area of the surrounding circuits. In reducing the area of surrounding circuits, it is important to reduce the write voltage and erase voltage from the viewpoint of ensuring the reliability along with miniaturization of the memory cell and reducing the circuit load of the surrounding circuits. Further, even in a system LSI, where there has been active development going on in recent years, it is becoming important to reduce the operating voltage from the viewpoint of mounting together with logic circuits.
Summarizing the problem, in a MONOS type nonvolatile semiconductor memory or other nonvolatile semiconductor memory with planarly dispersed charge storing means of the related art, setting the tunnel insulating film relatively thick in order to improve the disturbance characteristic limits the reduction of the operating voltage. That is, in a nonvolatile semiconductor memory of the related art, there is a tradeoff between making the tunnel insulating film thicker and reducing the operating voltage while maintaining a fast operating rate. Due to this, it suffers from the problem that it is not possible to simultaneously improve the disturbance characteristic and reduce the operating voltage.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a nonvolatile semiconductor memory such as a MONOS type nonvolatile semiconductor memory which operates by storing charges in planarly dispersed carrier traps and which has a better scaling of the tunnel insulating film than the FG type nonvolatile semiconductor memory, where it is possible to reduce the operating voltage while maintaining an excellent disturbance characteristic, and a process for the production of the same.
Another object of the present invention is to provide a write method in a nonvolatile semiconductor memory, including a bias setting method preferable to the cell structure.
According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a substrate; and a plurality of memory transistors formed in the substrate and arranged in a word direction and a bit direction, each memory transistor including: a semiconductor channel forming region formed in the substrate; a gate insulating film formed on the semiconductor channel forming region and comprising a Fowler-Nordheim (FN) type tunneling film which has a FN type tunneling electroconductivity and contains material having a dielectric constant greater than that of silicon oxide; a gate electrode formed on the gate insulating film; and a charge storing means, formed in the gate insulating film, and facing to the surface of the channel forming region.
The FN tunneling film comprises any one of a nitride film, an oxynitride film, and aluminum oxide film, a tantalum pentaoxide film and a BST (BaSrTiO
3
) film, having an FN tunneling electroconductivity.
The gate insulating film includes a buffer layer formed between the FN tunneling film and the channel forming region and suppressing an interface trap level.
The gate insulating film may comprise a Pool-Frenkel (PF) type film including any one of a nitride film, an oxynitride film, and aluminum oxide film, a tantalum pentaoxide film and a BST (BaSrTiO
3
) film, having an PN type electroconductivity.
The nonvolatile semiconductor memory device may further comprise a pull-up electrode in the vicinity of the gate electrode or a wiring layer connected to the gate electrode, via a dielectric film; and a pull-up gate bias means for applying a voltage to the pull-up electrode.
A plurality of gate electrodes of the plurality of memory transistors are connected to a plurality of word lines, and a selected transistor is connected between the pull-up gate bias means and the pull-up electrode, the pull-up gate bias means supplying a voltage having a polarity that is the same as a polarity of a boosting voltage for boosting the precharged word line by a capacitance coupling.
The pull-up electrode may be arranged in the vicinity of an upper portion of the gate electrode or a connection layer connecte
Kananen Ronald P.
Rader & Fishman & Grauer, PLLC
Vu Hung
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