Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-12
2004-04-27
Gurley, Lynne (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S629000, C438S631000, C438S633000, C438S643000, C438S645000, C438S653000, C438S660000, C438S672000, C438S687000, C438S692000
Reexamination Certificate
active
06727172
ABSTRACT:
BACKGROUND OF INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form copper contact, and interconnect structures.
(2) Description of Prior Art
To increase the performance of semiconductor devices, low resistivity copper has replaced traditionally used metals such as aluminum and tungsten, for use as contact structures, or for interconnect lines. The low resistivity of copper, again compared to other metals such as aluminum, or tungsten, has also allowed thinner and narrower metal structures to be used, allowing a greater number of smaller, and higher device density semiconductor chips to be obtained from a specific size starting substrate, thus reducing the fabrication cost of a specific semiconductor chip. The use of copper structures however can present specific problems not always encountered when using other metals. For example when copper is subjected to a chemical mechanical polishing, (CMP), procedure, to define a copper structure, or line, embedded in an opening in an insulator layer, damage, or defects in the copper structure can result. These defects in turn can present yield loss, as a result of opens or shorts, or reliability concerns in terms of electromigration. This invention will present a process sequence that will allow the copper layer to experience the CMP definition procedure, without defect generation. Prior art, such as Liu et al, in U.S. Pat. No. 6,015,749, show a method of fabricating copper structures, however that prior art does not describe the unique process sequence presented in this present invention, featuring unique preparation of the copper layer, prior to a subsequent CMP procedure.
SUMMARY OF THE INVENTION
It is an object of this invention to define a copper structure via a chemical mechanical polishing, (CMP), procedure.
It is another object of this invention to deposit a thin, compressive layer on a copper layer, prior to performing the CMP definition procedure.
It is still another object of this invention to perform a low temperature anneal, to a copper layer, and the overlying, thin compressive stress layer, prior to performing the CMP definition procedure.
In accordance with the present invention a method of reducing the defects in a copper structure, formed in an opening in an insulator layer, via a CMP procedure, is described. After creating an opening in an insulator layer, exposing a portion of the top surface of an underlying conductive region, a barrier layer is deposited, followed by the electro-chemical deposition, (ECD), of copper, completely filling the opening in the insulator layer. A thin, compressive stress layer is next deposited on the top surface of the copper layer, followed by a low temperature anneal. This combination results in the formation of nucleation sites, as well as optimum growth of copper grains, allowing a subsequent CMP procedure to remove regions of the thin barrier layer, and of the copper layer, from the top surface of the insulator layer, forming an embedded copper structure in the opening in the insulator layer. The embedded copper structure exhibits less defects than counterpart CMP defined copper structures, formed without the combination of a low compressive stress layer and a low temperature anneal.
REFERENCES:
patent: 5527739 (1996-06-01), Parrillo et al.
patent: 5976970 (1999-11-01), Dalal et al.
patent: 6015749 (2000-01-01), Liu et al.
patent: 6022808 (2000-02-01), Nogami et al.
patent: 6030895 (2000-02-01), Joshi et al.
patent: 6071810 (2000-06-01), Wada et al.
Chiou Wen-Chih
Jang Syun-Ming
Jong Shwangming
Ackerman Stephen B.
Gurley Lynne
Saile George O.
Taiwan Semiconductor Manufacturing Company
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