Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-07-11
2004-10-12
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S614000, C438S617000
Reexamination Certificate
active
06803303
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and packaging. More particularly, this invention relates to a semiconductor component having encapsulated bonded, interconnect contacts, to a method for fabricating the component, and to systems incorporating the component.
BACKGROUND OF THE INVENTION
Semiconductor components, such as chip scale packages, BGA devices, flip chip devices, and bumped dice include terminal contacts such as bumps, balls, pins or pads. The terminal contacts can be formed directly on the dice, or on substrates attached to the dice. Typically, the components also include protective layers which insulate one or more surfaces of the dice, and provide electrical insulation for the terminal contacts, and for conductors associated with the terminal contacts. The quality, reliability and cost of these types of components are often dependent on the fabrication method for the terminal contacts.
As the components become smaller, and the terminal contacts more dense, fabrication methods become more difficult. In particular, reliable electrical connections must be made between the terminal contacts for the components, and die contacts on the dice contained within the components. Typically, the die contacts are thin film aluminum bond pads in electrical communication with integrated circuits. The intermediate connections between the die contacts and the terminal contacts are referred to herein as “interconnect contacts”.
One type of interconnect contact comprises wires bonded at one end to the die contacts, and at an opposing end to bonding pads in electrical communication with the terminal contacts. These interconnect contacts are relatively fragile and can separate from the die contacts and become entangled. Another type of interconnect contact includes conductors on a polymer substrate, similar to TAB tape, attached to the face of the dice. In this case the polymer substrate may be difficult to align and attach to the dice.
In addition to forming reliable interconnect contacts between the die contacts and the terminal contacts, it is preferable that the fabrication method be performed at the wafer level wherein multiple components are fabricated on a substrate, such as a wafer or a panel, which can then be singulated into individual components. Further, it is preferable that the fabrication method be capable of being performed using conventional equipment and materials.
The present invention is directed to an improved semiconductor component, and to a wafer level method for fabricating the component, in large volumes, at low costs, and with minimal defects.
SUMMARY OF THE INVENTION
In accordance with the present invention an improved semiconductor component, a method for fabricating the component, and systems incorporating the component are provided.
The component includes a semiconductor die having a pattern of die contacts, such as bond pads or redistribution pads, in electrical communication with integrated circuits contained on the die. The component also includes interconnect contacts bonded to the die contacts, and encapsulated in an insulating layer. The interconnect contacts can comprise posts, studs, bumps, balls or ribbons formed using conventional equipment. The component also includes terminal contacts bonded directly to the interconnect contacts. In addition, the interconnect contacts can include metallization layers to facilitate bonding of the terminal contacts.
An alternate embodiment component includes a pattern of conductors on the insulating layer in physical contact with the interconnect contacts, and having bonding pads for the terminal contacts. In this embodiment the terminal contacts can have a pitch and a pattern that are different than the pitch and pattern of the die contacts. For example, the terminal contacts can have a fan out configuration relative to the die contacts and can be arranged in a dense area array, such as a ball grid array (BGA) or fine ball grid array (FBGA).
The method for fabricating the component includes the steps of providing a substrate containing multiple semiconductor dice, bonding the interconnect contacts to the die contacts, and forming an insulating layer on the dice configured to encapsulate the interconnect contacts while leaving the tip portions thereof exposed. The insulating layer can be formed by blanket deposition of a polymer material on the interconnect contacts, followed by etching back to a thickness that is less than a height of the interconnect contacts. Alternately, the insulating layer can be deposited on the interconnect contacts with a thickness that is less than the height thereof, such that the tip portions remain exposed, and an etch back step is not required. The method also includes the steps of forming the terminal contacts on the interconnect contacts, and singulating the substrate into a plurality of separate components.
A method for fabricating the alternate embodiment component includes the additional steps of forming the pattern of conductors on the insulating layer in electrical communication with the interconnect contacts, forming the terminal contacts in electrical communication with the conductors, and forming an insulating layer on the conductors.
In each embodiment, the component can be used to construct systems such as MCM packages, multi chip modules and circuit boards.
REFERENCES:
patent: 5908317 (1999-06-01), Heo
patent: 6048755 (2000-04-01), Jiang et al.
patent: 6091141 (2000-07-01), Heo
patent: 6118179 (2000-09-01), Farnworth et al.
patent: 6180504 (2001-01-01), Farnworth et al.
patent: 6252301 (2001-06-01), Gilleo et al.
patent: 6303997 (2001-10-01), Lee
patent: 6331737 (2001-12-01), Lim et al.
patent: 6365439 (2002-04-01), Miyazaki et al.
patent: 6368896 (2002-04-01), Farnworth et al.
patent: 6369454 (2002-04-01), Chung
patent: 6400172 (2002-06-01), Akram et al.
patent: 6429675 (2002-08-01), Bell
patent: 6465877 (2002-10-01), Farnworth et al.
patent: 6476503 (2002-11-01), Imamura et al.
patent: 6620731 (2003-09-01), Farnworth et al.
Farnworth Warren M.
Hiatt William M.
Sinha Nishant
Watkins Charles M.
Gratton Stephen A.
Nguyen Thanh
LandOfFree
Method of fabricating semiconductor component having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating semiconductor component having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating semiconductor component having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3261073