Semiconductor memory cell and method of forming same

Details Semiconductor memory cell and method of forming same Semiconductor memory cell and method of forming same

2002-12-02

2004-05-25

Abraham, Fetsum (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06740921

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory cell and more particularly to a random access memory (RAM) with high-speed, low-voltage operation that is also nonvolatile.
2. Description of Related Art
The nonvolatile memory market has undergone amazing expansion driven by the demand for mobile devices typified by cellular telephones. The flash memory is a typical nonvolatile memory but basically has a slow operating speed so is utilized as a programmable ROM (Read-Only-Memory). However a high speed DRAM (Dynamic RAM) is required as a work memory. Both a flash and DRAM are contained in the cellular telephone memory. If a device could be achieved having the characteristics of these two memories, then not only could a flash and DRAM be mounted on the same chip but all semiconductor memories could be replaced to render an extremely large impact.
One memory of this type, a memory utilizing phase changes (OUM: Ovonic Unified Memory) was proposed by the Intel Corporation at the 2001 IEDM (International Electron Device Meeting).
The operating principle of this memory is simply described as follows. The OUM utilizes a material called chalcogenide as a memory node to store different resistance values according to the state of crystallization. Chalcogenide is a material utilized as a medium in DVD and CDs. This is typically in the form of alloys such as Ag—In—Sb—Te or Ge—Sb—Te containing at least antimony (Sb) and tellurium (Te). A basic memory cell is composed of a select transistor and chalcogenide, and resembles the so-called DRAM cell. The chalcogenide can be regarded as a substitute for the capacitor. The crystallized state of the chalcogenide is monocrystalline or amorphous and the difference in resistance value varies from 10 to 10,000 times. A solid state memory can be obtained by utilizing this difference. In the case of the MRAM (Magnetic Ram) gaining much recent attention as a nonvolatile memory, the rate of change in resistance is about 40 percent. The OUM can therefore easily perform much greater sensing than the MRAM.
The Joule heat generated by applying a voltage is utilized to change the crystallization state of the chalcogenide. In the amorphous state, the chalcogenide is heated to approximately 600 degrees Centigrade to melt it and then quickly cools. In the crystallized state, a temperature of 400 degrees Centigrade is maintained for about 50 nanoseconds. A pulse as shown in
FIG. 2
is therefore applied to write data. To read data, the word line is set to on, and information of two values (“0”, “1”) is identified by the current flow (between the common ground and bit line).
The phase changing (Ovonic) memory described above comprising a select transistor and chalcogenide has a cell surface area of approximately 8F
2
or more. The value F here denotes the minimum processing dimensions. The problem therefore exists that in order to increase its capacity, the memory cell surface area must be reduced even further.
SUMMARY OF THE INVENTION
To resolve the aforementioned problems with the present invention, the present invention has the object of providing a memory cell structure and forming method for that memory cell utilizing a vertical transistor and capable of achieving a memory cell with a surface area of 4F
2
. A typical memory cell structure of the present invention is shown in FIG.
1
. The memory cell structure in the figure, from the top on downwards is composed of a first wiring layer (
7
) for reading and writing, a vertical select transistor (
1
) electrically connected to that wiring layer, a chalcogenide material (
2
) above it for accumulating information, and a second wiring layer (
8
) for reading and writing on the chalcogenide material. The flat layout of the memory cell of the invention is shown in FIG.
3
. The cell wiring layer (
803
) and the word line (
403
) are formed at a minimum pitch 2F so the memory cell surface area is 4F
2
.


REFERENCES:
patent: 4845533 (1989-07-01), Pryor et al.
patent: 5032538 (1991-07-01), Bozler et al.
patent: 5920788 (1999-07-01), Reinberg
patent: 6087674 (2000-07-01), Ovshinsky et al.
patent: 6429449 (2002-08-01), Gonzalez et al.
patent: 6437383 (2002-08-01), Xu et al.
Stefan Lai, Tyler Lowrey, “Oum—A 180 nm Nonvolatile Memory Cell Element Technology For Stand Alone and Embedded Applications”, 2001, IEDM Technical Digest Paper, pp. 36.5.

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