Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2002-05-15
2004-04-13
Perveen, Rehana (Department: 2824)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S023000, C710S033000, C710S035000, C711S100000, C711S101000, C711S102000, C711S103000
Reexamination Certificate
active
06721820
ABSTRACT:
FIELD AND BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and method for using specialized flash controllers to increase the read and write performance of a flash-based storage system.
2. Description of the Related Art
Existing flash-based storage systems employ different kinds of logic to provide data and control signals to the flash array. One of the methods (which has been used by M-Systems Flash Disk Pioneers, Tel Aviv, Israel, for several years) is to have a dedicated controller that is connected from one side to the CPU data, address buses and control signals, and from the other side to the flash components to which it provides required signals. The CPU accesses the flash controller and flash array through a “window” in the memory. Read and write accesses to some addresses are decoded by the controller as accesses to its internal registers, such as configuration registers, chip selector registers, status registers or ECC registers. Accesses to others addresses are decoded as accesses directly to the flash array. For example, when a CPU wishes to perform a read operation from a particular flash chip, it
a) Sets the chip selector register to point onto that particular chip;
b) Sends the read command to the selected chip (if necessary, specifying Command or Address mode in the relevant controller's registers and the writing command and/or address into the flash array window);
c) Waits for the flash chip to become Ready (to read data from it); and
d) Reads the data from the flash array window to RAM
One of the limitations of this system is that when the flash array is treated as a memory-like device, the CPU cannot use “fly-by” Direct Memory Access (DMA) operations for the data transfer. Direct Memory Access (DMA) is a capability provided by some computer bus architectures that allows data to be sent directly from an attached device (such as a disk drive) to the memory on the computer's motherboard. The microprocessor is freed from involvement with the data transfer, thus speeding up overall computer operation. (Winn L. Rosch, The Winn L. Rosch Hardware Bible (Third Edition), Sams Publishing, 1994, Last update: Oct. 13, 1999) If two memory-like devices are involved in the transfer (such as flash array and RAM), “fly-by” transfer is not possible, since the system can only indicate either a Read or a Write operation at one particular time, so it can not indicate the direction of the transfer for 2 devices simultaneously. For that reason, all DMA transfers between 2 memory-like devices are “buffered”: during each DMA cycle the DMA controller first reads from one device, then writes that data into the other device. When DMA transfer is between memory-like device and DMA-capable Input/Output (I/O) device, during each DMA cycle the data is read from one device and written into the other. Such operation is possible because the memory-like devices follow the system-bus Read and Write signals, while the DMA-capable I/O device knows the direction (read or write) of the transfer by other means. Clearly the “fly-by” mode is faster than the “buffered” one.
Another limitation of the existing system is that the system is idle when the flash array is in “Not Ready” state. When the flash chip with page access is given a command to read a page, it requires time for its internal processing. During this time the system cannot transfer information to or from flash, or execute other operations with it, and is therefore required to wait until the conclusion of the “Not Ready” state. Likewise, after being given a command to write a page, or erase a block, the flash chip performs internal processing, during which it is in “Not Ready” state. During this time the system can not transfer information to or from flash, or execute other operations with it, and hence is not operating at full efficiency.
Yet another limitation of the existing system is the way the data is copied. During the normal functioning of the flash storage system, some pages should be copied from one block to another block. In existing systems, data is first read from the source page into the intermediate RAM buffer, and consequently it is written into the destination page. Such a method is not fully efficient, since the data is transferred twice.
There is thus a widely recognized need for, and it would be highly advantageous to have, a system and method for adding DMA capability to the flash controller so that faster “fly-by” DMA transfers from or to the flash array will be possible.
There is a further need for a method to transfer data or otherwise continue operation of the flash system, while a flash chip is in “Not Ready” state.
There is a further need for a method to enable direct transfer of data from one flash chip into another flash chip, without necessarily being read into the intermediate RAM buffer, thus reducing the time of the copy operation.
SUMMARY OF THE INVENTION
According to the present invention there is provided a system and method for using specialized flash controllers to increase the read and write performance of a flash-based storage system.
The present invention provides solutions for the limitations described above, by describing a method to add the DMA capability to the flash controller, so that faster “fly-by” DMA transfers from or to the flash array will be possible.
In an additional embodiment, the present invention describes a method to employ several flash controllers so that while one or more flash chips are “Not Ready”, others are able to transfer data or otherwise continue operation of the flash system.
In a further embodiment, the present invention describes a method to employ several flash controllers with DMA functionality so that data will be transferred directly from one flash chip into another flash chip (in one action), without necessarily being read into the intermediate RAM buffer, thus reducing the time of the copy operation.
An addition embodiment of the present invention describes a method for combining the functionality of several flash controllers into one multi-controller, which simplifies the design of the flash-based storage system.
The present invention thus consists of four primary methods. First, a way to use several flash controllers is described, so that page-programming time and page read time are effectively reduced. Secondly, there is described a DMA interface to the flash controller, which reduces the data transfer cycle. Thirdly, there is described a way to use several flash controllers so that the page copy time will effectively be reduced. Fourthly, there is provided a way to combine the functionality of several flash controllers into one multi-controller.
In its preferred mode, the present invention comprises a solid-state storage system with a plurality of flash controllers or a multi-controller with DMA interface, organized in a way that reduces the page programming and page copy time.
REFERENCES:
patent: 5640349 (1997-06-01), Kakinuma et al.
patent: 5812814 (1998-09-01), Sukegawa
patent: 5822251 (1998-10-01), Bruce et al.
patent: 5956743 (1999-09-01), Bruce et al.
patent: 6131139 (2000-10-01), Kikuchi et al.
Winn L. Rosch, The Winn L. Rosch Hardware Bible (Third Edition), Sams Publishing 1994, Last update Oct. 13, 1999.
Yaroshetsky Alex
Zilberman Eugene
Friedman Mark M.
M-Systems Flash Disk Pioneers Ltd.
Perveen Rehana
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