Field bus interface board

Details Field bus interface board Field bus interface board

2001-09-25

2004-01-06

Perveen, Rehana (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Flow controlling

C710S033000, C710S052000, C710S305000, C710S310000

Reexamination Certificate

active

06675236

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a field bus interface board, and more particularly to a field bus interface board for performing a digital communication between various kinds of sensors and actuators in control fields.
2. Description of the Prior Art
Recently, field bus interface techniques have been proposed and used for interfacing with digital serial communication devices or methods used in control fields for factory automation, in other words, for controlling control machines, sensors, and actuators.
FIG. 1
is a block diagram showing a conventional field bus interface board.
Referring to
FIG. 1
, the conventional field bus interface board includes a microcontroller
1
, latches
2
and
2
a
, a first decoder
5
, a first bi-directional bus transceiver
6
, a second bi-directional bus transceiver
6
a
, a Manchester encode/decoder
9
, first and second latch/shift registers
7
and
8
, an interface
10
, a CRC generator/checker
11
, and a personal computer interface
12
. The microcontroller
1
has a ROM
1
a
storing programs for information exchange and an input/output port, and outputs an address for storing information data and an address latch enable signal ALE. The latches
2
and
2
a
separate the address received by the microcontroller
1
into lower bytes and higher bytes addresses LOW ADDR and HIGH ADDR, respectively, and latch them for a predetermined period of time, in response to the address latch enable signal ALE. The first decoder
5
decodes the lower and high bytes addresses received through the latches
2
and
2
a
, and outputs a chip select signal CS to a chip select terminal of a system RAM
3
or a dual-port RAM
4
. The first bus transceiver
6
transmits lower bytes data LOW DATA received by the microcontroller
1
to the system RAM
3
and the dual-port RAM
4
. The second bus transceiver
6
a
transmits higher bytes data HIGH DATA received by the microcontroller
1
to both the system RAM
3
and the dual-port RAM
4
. The Manchester encoder/decoder
9
Manchester-encodes an input data or Manchester-decodes the Manchester-encoded data. The first and second latch/shift registers
7
and
8
are commonly connected to the system RAM
3
, the dual-port RAM
4
and the Manchester encoder/decoder
9
. The interface
10
matches data transmitted/received between the Manchester encode/decoder
9
and a field bus (not shown). The CRC generator/checker
11
checks whether an error is generated in data. The personal computer interface
12
interfaces with a computer (not shown) for transmitting and receiving data.
The conventional field bus interface board having the above construction controls its operation and field bus communication under the control of the microcontroller
1
. Accordingly, the conventional field bus interface board is problematic in that the microcontroller performs the operation of the board itself and field bus communication with a softwareable method simultaneously, thus complicating its construction, and increasing data amounts to be processed by the microcontroller, and thereby, decreasing the processing speed of the interface board.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above problem, and it is an object of the present invention to provide a field bus interface board for improving its processing speed and its communication speed by simplifying its construction and reducing a load of its control unit.
In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a field bus interface board installed in a computer and connected to a field bus line, comprising a main controller for controlling an entire operation of the field bus interface board; a field bus controller for controlling a data transmission and reception though the field bus line; a dual-port memory shared between the computer and the main controller for exchanging data with the computer; a buffer memory for buffering data transmitted to the field bus line or received from the field bus line, under the control of the field bus controller; and a field bus interfacing means for transmitting data to the field bus line or receiving data from the field bus line, under the control of the field bus controller.


REFERENCES:
patent: 5758075 (1998-05-01), Graziano et al.
patent: 5764891 (1998-06-01), Warrior
patent: 6105086 (2000-08-01), Doolittle et al.
patent: 6151640 (2000-11-01), Buda et al.
patent: 6463338 (2002-10-01), Neet

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