Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2002-08-27
2004-05-11
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S780000
Reexamination Certificate
active
06734568
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of the priorities from the prior Japanese Patent Applications No. 2001-259310 filed on or around Aug. 29, 2001 and No. 2001-298252 filed on or around Sep. 27, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device and a method of manufacturing the same, and more particularly relates to a semiconductor device including a bump electrode provided on an electrode via an under bump metal film, and a method of manufacturing such a semiconductor device. Further, the invention relates to a semiconductor device in which substrates are joined, semiconductor substrates are joined, and the substrate and the semiconductor substrate are joined, and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
As semiconductor chips constituting semiconductor devices are being highly integrated and improved in their functions, a variety of methods have been developed and applied in order to connect external connection electrodes (i.e. bonding pads) of the semiconductor chips to electrodes of a wiring substrate (i.e. a printed circuit board) on which the semiconductor chips are mounted. There have been strong demands for highly integrated semiconductor chips such as IC (integrated circuit) chips and LSI (large scale integrated circuit) chips to be compatible with high speed circuit operation, efficient heat diffusion, and accommodation of multiple terminals (pins). Recently, it is anticipated that high-end semiconductor chips are required to have several thousands of external connection electrodes (terminals).
Further, semiconductor devices have been required to be compact in size and light in weight, and to perform multiple functions in the view of a system side. In order to satisfy the foregoing requirements, it is inevitable to mount semiconductor chips in an extensively integrated state on the wiring substrate. A multiple chip structure or a three-dimensional mounting structure is being studied in order to meet requirements for multiple functions.
The flip chip (FC) method or tape-automated bonding method (TAB) using bump electrodes is advantageous in order to increase terminals. In the FC method, bump electrodes are provided at least at either external connection electrodes of the semiconductor chip or electrodes of the wiring substrate, and the bump electrodes and electrodes are connected, or the bump electrodes are mutually connected. For instance, in a semiconductor chip having an extremely large number of high-end terminals, a plurality of solder bump electrodes are arranged in the shape of a lattice on a surface (circuit mounding surface) of the semiconductor chip. The semiconductor chip is faced with a surface of the wiring substrate, and is mounted thereon. Thereafter, solder reflow is performed in order to join soldering bump electrodes and the wiring substrate, so that the semiconductor chip is mounted on the wiring substrate.
In the case of the TAB method, gold (Au) bump electrodes are provided on external connection terminals of the semiconductor chip, and copper (Cu)/tin (Sn) bump electrodes are formed on electrodes of the wiring substrate. Thereafter, the bump electrodes are positioned with respect to leads of the wiring substrate, and the Au bump electrodes are joined to the Sn/Cu bump electrodes by full thermo-compression. In this state, the semiconductor chips are completely mounted on the wiring substrate.
Minute bump electrodes are usually made by a plating process, as shown in FIG.
15
(A) to FIG.
15
(D) of the accompanying drawings.
(1) First of all, a semiconductor wafer
100
is prepared (see FIG.
15
(A)). The semiconductor wafer
100
is in a state prior to the dicing into semiconductor chips. An external connection electrode (bonding pad)
101
is provided on the semiconductor wafer
100
at a position where a semiconductor chip is to be formed. A passivation film
102
is present on the external connection electrode
101
, and has an aperture
102
H. A polyimide group resin film
103
extends over a bump electrode forming region on the passivation film
102
, and has an aperture
103
H.
(2) An under bump metal (UBM) film
110
is formed all over the semiconductor wafer
100
, i.e. on the polyimide group resin film
103
, passivation film
102
, an inner wall of the aperture
103
H, an inner wall of the aperture
102
H, and the external connection electrode
101
which is exposed from the apertures
103
H and
102
H. The UBM film
110
is applied by the sputtering, plating or the like, and is required to perform the following.
(a) To keep the external connection electrode
101
and Au bump electrode
112
(see FIG.
15
(B)) electrically conductive;
(b) To keep the external connection electrode
101
and bump electrode
112
in close contact with each other;
(c) To function as a barrier for preventing heat diffusion between the external connection electrode
101
and the bump electrode
112
, and preventing reduced conduction and adhesion depending upon time; and
(d) To function as a feeding layer during the plating.
In order to meet these requirements, the UBM film
110
includes two or three stacked layers. For instance, the UBM film
110
is constituted by a titanium (Ti) layer, a nickel (Ni) layer and a palladium (Pd) layer which are stacked one over after another, or a chromium (Cr) layer, a Cu layer and an Au layer which are stacked one over after another, when observed from the external connection electrode
101
to the bump electrode. Further, the UBM film
110
is required to be several hundred nm to several &mgr;m thick.
(3) A photoresist film is applied onto the UBM film
110
, and is exposed and developed by the photolithography process. A bump electrode-forming mask
111
is made using the photoresist film (refer to FIG.
15
(B)). The mask
111
has an aperture
111
H via which the UMB film
110
has its surface exposed on the external connection electrode
101
.
(4) Electricity is supplied to the UBM film
110
by the electrolytic plating, so that the Au bump electrode
112
is formed on the UBM film
110
in the aperture
111
H of the bump electrode-forming mask
111
. Refer to FIG.
15
(B).
(5) Thereafter, the bump electrode-forming mask
111
is stripped as shown in FIG.
15
(C).
(6) The UBM film
110
is etched using the Au bump electrode
112
as an etching mask, and has its unnecessary part removed. For instance, when the UBM film
110
is constituted by the Ti, Ni and Pd layers, the Pd and Ni layers are wet-etched using a composite solution containing nitric acid, hydrochloric acid and acetic acid. Thereafter, the Ti layer is wet-etched using a fluoride acid solution.
A solder bump electrode made of lead (Pb)—Sn, silver (Ag)—Sn or the like are manufactured as shown in FIG.
16
(A) to FIG.
16
(E).
(1) First of all, a semiconductor wafer
100
is prepared as shown in FIG.
16
(A), similarly to the foregoing Au bump electrode
112
. An external connection electrode
101
is provided over a semiconductor chip forming regions of the semiconductor wafer
100
. A passivation film
102
having an aperture
102
H, and a polyimide group resin film
103
having an aperture
103
H are formed over the external connection electrode
101
.
(2) Referring to FIG.
16
(A), a UBM film
110
is formed on the semiconductor wafer
100
and the external connection electrode
101
. This UBM film
110
has the stacked structure similarly to the Au bump electrode
112
. However, the UBM film
110
is thicker the UBM film
110
in the foregoing case in order to prevent diffusion of Sn from a solder bump electrode
122
to the external connection electrode
101
.
(3) Thereafter, a bump electrode-forming mask
121
is formed on the UBM film
110
using the photolithography process (refer to FIG.
16
(B)). The bump electrode-forming mask
121
has an aperture
121
H via which the front surface of the UBM film
110
is exposed on the
Ezawa Hirokazu
Matsuo Mie
Miyata Masahiro
Clark Sheila V.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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