Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-07-31
2004-07-27
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S163000
Reexamination Certificate
active
06767776
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to semiconductor devices and methods for manufacturing the same, and more particularly to a semiconductor device that can restrict the substrate floating effect even in a transistor having a short gate length and long gate width.
2. Discussion
FIG.
11
(
a
) shows a plan view of one example of a conventional semiconductor device, and FIG.
11
(
b
) shows a cross-sectional view taken along lines
11
b
—
11
b
indicated in FIG.
11
(
a
). The semiconductor device includes a transistor with a SOI (Silicon On Insulator) structure.
As shown in FIG.
11
(
b
), the SOI substrate
104
is formed from a supporting substrate
101
composed of single crystal silicon (Si), an embedded oxide film (BOX layer)
102
formed on the supporting substrate
101
, and a single crystal Si layer
103
that is formed on the embedded oxide film
102
. The SOI substrate
104
can be manufactured by a variety of manufacturing methods, for example, it can be manufactured by a bonding method, a SIMOX (Separation by Implanted Oxygen) method.
An element isolation oxide film
6
is formed in the single crystal Si layer
103
. A gate oxide film
109
is formed on the surface of the single crystal Si layer
103
, and a gate electrode
105
is formed on the gate oxide film
109
. Sidewalls
110
are formed on side walls of the gate electrode
105
, and impurity diffusion layers
111
with a low impurity concentration are formed in the single crystal Si layer
103
below the sidewalls. Diffusion layers
107
and
108
for source/drain regions are formed in the single crystal Si layer
103
adjacent to the low impurity concentration diffusion layers
111
.
The single crystal Si layer
103
under the gate electrode
105
defines a body region
112
. The body region
112
extends outwardly from one end of the gate electrode
105
as shown in FIG.
11
(
a
). The gate electrode
105
and the diffusion layers
107
and
108
for the source/drain regions are connected to external elements through contact sections
113
115
, respectively. Also, the body region
112
is connected to a body terminal (not shown) through a contact section
116
.
By the application of a specified voltage to the body region through the body terminal, the body potential is fixed and thus the substrate floating effect is controlled. The body potential is fixed because the state of the body potential is always unstable in operating the transistor unless the body potential is fixed, which substantially affects the transistor characteristics.
The conventional semiconductor device explained above is formed with a short gate length and a long gate width as shown in FIG.
11
(
a
). In the semiconductor device having such a configuration, the body potential in an area that is far from the contact section
116
for fixing the body potential cannot be completely removed, and the substrate floating effect may occur. In other word, in a semiconductor device having a short gate length and a long gate width, the resistance in the body region is high. As a result, the body potential cannot be sufficiently fixed, and the substrate floating effect may occur.
Also, in the conventional semiconductor device described above, the body region extends out from one end of the gate electrode in order to form a contact section therein for fixing the body potential. However, as the body region is extended in this manner, the area occupied by the element increases, which is problematical because it hinders miniaturization of elements.
The present invention has been made in view of the circumstances described above, and its object is to provide a semiconductor device that can restrict the substrate floating effect even in a transistor having a short gate length and long gate width, and a method for manufacturing the same.
SUMMARY OF THE INVENTION
To solve the problems described above, a semiconductor device in accordance with the present invention is characterized in comprising:
a gate electrode formed on a dielectric film;
a gate dielectric film formed on the gate electrode;
a body region composed of epitaxial Si formed on the gate dielectric film;
a diffusion layer for source/drain regions formed on both sides of the body region; and
a body terminal connected to the body region for applying a specified potential to the body region.
The above semiconductor device has a structure in which the body region is disposed over the gate electrode, whose upper and lower positions are mutually reversed compared to a conventional semiconductor device. For this reason, a body terminal can be readily connected to any portion of the body region. As a result, when a transistor has a short gate length and a long gate width, plural contact sections may be disposed on the body region to the extent that the substrate floating effect does not occur, such that the substrate floating effect is sufficiently suppressed.
A semiconductor device in accordance with the present invention is characterized in comprising:
a single crystal Si layer formed on a dielectric film;
a first opening section formed in the single crystal Si layer;
an interlayer dielectric film formed in the first opening section;
a second opening section formed in the interlayer dielectric film;
a gate electrode formed in the second opening section;
a gate dielectric film formed on the gate electrode;
an epitaxial Si layer formed on the gate dielectric layer;
a body region formed in the epitaxial Si layer;
a diffusion layer for source/drain regions formed in the epitaxial Si layer and located on both sides of the body region; and
a body terminal connected to the body region for applying a specified potential to the body region.
Also, the semiconductor device in accordance with the present invention may preferably further include a supporting substrate formed below the dielectric film.
Further, the semiconductor device in accordance with the present invention may further include a third opening section located around a source/drain forming region formed in the epitaxial Si layer, and a dielectric layer embedded in the third opening section.
A method for manufacturing a semiconductor device in accordance with the present invention is characterized in comprising the steps of:
forming a gate electrode on a dielectric film;
forming a gate dielectric film on the gate electrode;
forming an epitaxial Si layer on the gate dielectric film;
forming a body region in the epitaxial Si layer;
forming a diffusion layer for source/drain regions on both sides of the body region in the epitaxial Si layer; and
forming a body terminal on the body region for applying a specified potential to the body region.
The above method for manufacturing a semiconductor device provides a structure in which the body region is disposed over the gate electrode through the gate dielectric film, whose upper-lower positions are mutually reversed compared to those of conventional semiconductor devices. For this reason, after the step of forming the diffusion layer for source/drain regions, the upper surface of the body region is entirely exposed, which makes it easy to connect a body terminal to any portion of the body region. As a result, when a transistor has a short gate length and a long gate width, plural contact sections may be disposed over the body region to the extent that the substrate floating effect does not occur, and thus the substrate floating effect is sufficiently suppressed.
A method for manufacturing a semiconductor device in accordance with the present invention is characterized in comprising the steps of:
preparing a SOI substrate composed of a supporting substrate, a dielectric film and a single crystal Si layer;
forming a first opening section in the single crystal Si layer at a position around a gate electrode forming region;
embedding an interlayer dielectric film in the first opening section;
forming a second opening section in the single crystal Si layer at a position around a gate electrode forming region;
forming a gate electrode in the second opening section;
formi
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