Method of reading stored data and semiconductor memory device

Details Method of reading stored data and semiconductor memory device Method of reading stored data and semiconductor memory device

2002-03-25

2004-05-18

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S189110

Reexamination Certificate

active

06738283

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of reading stored data and a semiconductor memory device, more particularly relates to a method of reading data stored in a semiconductor memory device including a static type random access memory (RAM) and such a semiconductor memory device and to a semiconductor memory device including a static type content addressable memory (CAM).
2. Description of the Related Art
First, an explanation will be made of a static RAM (SRAM) and a CAM having a SRAM type memory circuit.
(SRAM)
SRAMs enable high speed read and write operations and, at the same time, eliminate the need for a refresh operation of the stored data as with a dynamic RAM (DRAM) and enable streamlining of peripheral circuits. Due to these advantages, they are being widely used as cache memories, memories of portable terminals, and other relatively small capacity memory devices for which high speed operation and streamlining are required.
As basic configurations of a memory cell of an SRAM (hereinafter referred to as an “SRAM cell”), a six-transistor type SRAM cell using six transistors and a four-transistor type SRAM cell omitting the load transistors of this six-transistor type SRAM cell are generally known.
First, an explanation will be made of the six-transistor type SRAM cell.
FIG. 23
is a circuit diagram of a six-transistor type SRAM cell. The SRAM cell shown in
FIG. 23
has an n-type MOS transistor Qn
1
a
to n-type MOS transistor Qn
1
d
and a p-type MOS transistor Qp
1
a
and p-type MOS transistor Qp
1
b.
Drains of the p-type MOS transistor Qp
1
a
and the n-type MOS transistor Qn
1
c
are connected to a node N
1
a
, while their gates are connected to a node N
1
b
. Also, a source of the p-type MOS transistor Qp
1
a
is connected to a power supply voltage Vcc, while the source of the n-type MOS transistor Qn
1
c
is connected to a reference potential. These p-type MOS transistor Qp
1
a
and n-type MOS transistor Qn
1
c
form one CMOS inverter using the node N
1
b
as an input and using the node N
1
a
as an output.
The drains of the p-type MOS transistor Qp
1
b
and the n-type MOS transistor Qn
1
d
are connected to the node N
1
b
, while their gates are connected to the node N
1
a
. Also, the source of the p-type MOS transistor Qp
1
b
is connected to the power supply voltage Vcc, while the source of the n-type MOS transistor Qn
1
d
is connected to the reference potential. These p-type MOS transistor Qp
1
b
and n-type MOS transistor Qn
1
d
form one CMOS inverter using the node N
1
a
as an input and using the node N
1
b
as an output.
The inputs and outputs of the CMOS inverter comprised by the p-type MOS transistor Qp
1
a
and the n-type MOS transistor Qn
1
c
and the CMOS inverter comprised by the p-type MOS transistor Qp
1
b
and the n-type MOS transistor Qn
1
d
are connected to each other in the form of a ring, whereby one memory circuit is comprised.
The gate of the n-type MOS transistor Qn
1
a
is connected to a word line WORD, its drain is connected to a bit line BIT, and its source is connected to the node N
1
a.
The gate of the n-type MOS transistor Qn
1
b
is connected to the word line WORD, its drain is connected to an inverted bit line BITB, and its source is connected to the node N
1
b.
Next, an explanation will be made of the read operation and the write operation of a six-transistor type SRAM cell having the above configuration.
The stored data of the SRAM cell is stored in the memory circuit by the CMOS inverter in either of a state where the node N
1
a
is at high level and the node N
1
b
is at the low level or a state where the node N
1
a
is at the low level and the node N
1
b
is at the high level. During a period where this stored data is held, the word line WORD is set at the low level, and the n-type MOS transistor Qn
1
a
and the n-type MOS transistor Qn
1
b
are brought to a cutoff state. By this, the memory circuit and the bit line are separated, so the stored data is held.
When reading the stored data of the SRAM cell, the bit line BIT and the inverted bit line BITB are pulled up to the power supply voltage Vcc in advance by a not illustrated pullup circuit. The word line WORD is set to a high level in this state. By this, the n-type MOS transistor Qn
1
a
and the n-type MOS transistor Qn
1
b
become conductive, and the voltage of the bit line BIT or the inverted bit line BITB changes in accordance with the stored data.
For example, when the node N
1
a
is at the high level and the node N
1
b
is at the low level, since the bit line BIT and the node N
1
a
have almost equal voltages, no current flows through the n-type MOS transistor Qn
1
a
and the potential of the bit line BIT remains at the power supply voltage Vcc as it is and does not change, but the inverted bit line BITB has a high voltage in comparison with the node N
1
b
, so the current flows from the inverted bit line BITB to the node N
1
b
and the potential of the inverted bit line BITB falls. The potential difference (or current difference) between these bit line BIT and inverted bit line BITB is amplified by a not illustrated differential amplifier circuit and output to a data line.
When writing the stored data of the SRAM cell, the word line WORD is set at the high level in a state where either of the bit line BIT or the inverted bit line is pulled down to the reference potential and the other is pulled up to the power supply voltage Vcc in accordance with the data to be written. By this, the node N
1
a
and the node N
1
b
are set to potentials in accordance with the write data.
Next, an explanation will be made of a four-transistor type SRAM cell.
FIG. 24
is a circuit diagram of a four-transistor type SRAM cell. The SRAM cell shown in
FIG. 24
has an n-type MOS transistor Qn
2
a
, n-type MOS transistor Qn
2
b
, p-type MOS transistor Qp
2
a
, and p-type MOS transistor Qp
2
b.
The drain of the n-type MOS transistor Qn
2
a
is connected to a node N
2
a
, its gate is connected to a node N
2
b
, and its source is connected to the reference potential.
The drain of the n-type MOS transistor Qn
2
b
is connected to a node N
2
b
, its gate is connected to a node N
2
a
, and its source is connected to the reference potential.
The gate of the p-type MOS transistor Qp
2
a
is connected to a word line WORDB, its source is connected to the bit line BIT, and its drain is connected to the node N
2
a.
The gate of the p-type MOS transistor Qp
2
b
is connected to the word line WORDB, its source is connected to the bit line BITB, and its drain is connected to the node N
2
b.
The inputs and outputs of the inverter by the n-type MOS transistor Qn
2
a
and the inverter by the n-type MOS transistor Qn
2
b
are connected to each other in the form of a ring, whereby one memory circuit is comprised. Also, the size of transistors is set so that a leakage current in the off state of the p-type MOS transistor Qp
2
a
and the p-type MOS transistor Qp
2
b
becomes larger than the leakage current of the n-type MOS transistor Qn
2
a
and the n-type MOS transistor Qn
2
b
, charges are supplied from the bit line BIT and the inverted bit line BITB which are pulled up to the power supply voltage Vcc to the node N
2
a
and the node N
2
b
by this, and the stored data of the memory circuit is held constant.
Next, an explanation will be made of a read operation and write operation of a four-transistor type SRAM cell having the above configuration.
The stored data of the SRAM cell is stored in the memory circuit of the two transistors mentioned above in either of the state where the node N
2
a
is at the high level and the node N
2
b
is at the low level or the state where the node N
2
a
is at the low level and the node N
2
b
is at the high level. During the period where this stored data is held, the word line WORDB is set at the high level and the p-type MOS transistor Qp
2
a
and the p-type MOS transistor Qp
2
b
are brought to a cutoff state and, at the same time, the bit line BIT and the inverted bit line BITB are pulled up to the power sup

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