High density dual bit flash memory cell with non planar...

Details High density dual bit flash memory cell with non planar... High density dual bit flash memory cell with non planar...

2002-06-07

2004-05-11

Whitehead, Jr., Carl (Department: 2813)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280, C438S981000

Reexamination Certificate

active

06735123

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to flash memory cell devices and more specifically, to improvements in fabricating a dielectric memory cell structure for dual bit storage.
BACKGROUND OF THE INVENTION
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO
2
), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate are a channel region positioned below the vertical stack and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Si—SiO
2
energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the Si—SiO
2
interface under the influence of the control gate electrical field and gain sufficient energy to cross the barrier.
Once programmed, the negative charge on the floating gate increases the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate. During a “read” of the memory cell, the magnitude of the current flowing between the source and drain at a predetermined control gate voltage indicates whether the flash cell is programmed.
More recently dielectric memory cell structures have been developed. A conventional dielectric memory cell
10
is shown in cross section in FIG.
1
and is characterized by a vertical stack of an insulating tunnel dielectric layer
12
, a charge trapping dielectric layer
14
, an insulating top oxide layer
16
, and a polysilicon control gate
18
positioned on top of a crystalline silicon substrate
15
. Within the substrate
15
are a channel region
17
positioned below the vertical stack and source diffusion
19
and drain diffusion
23
on opposing sides of the channel region
17
. This particular structure of a silicon channel region
17
, tunnel oxide
12
, nitride
14
, top oxide
16
, and polysilicon control gate
18
is often referred to as a SONOS device.
Similar to the floating gate device, the SONOS memory cell
10
is programmed by inducing hot electron injection from the channel region
17
to the nitride layer
14
to create a non volatile negative charge within charge traps existing in the nitride layer
14
. Again, hot electron injection can be achieved by applying a drain-to-source bias along with a high positive voltage on the control gate
18
. The high voltage on the control gate
18
inverts the channel region
17
while the drain-to-source bias accelerates electrons towards the drain region
23
. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Si—SiO
2
energy barrier between the channel region
17
and the tunnel oxide
12
. While the electrons are accelerated towards the drain region
23
, those electrons which collide with the crystalline lattice are re-directed towards the Si—SiO
2
interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier. Because the nitride layer stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a drain charge storage region
13
that is close to the drain region
23
(or in a source charge storage region
11
that is close to the source region
19
if a source to drain bias is used) from which the electrons were injected. As such, the SONOS device can be used to store two bits of data, one in each of the charge storage regions
11
and
13
, per cell and are typically referred to as dual bit SONOS devices.
A problem associated with hot carrier injection programming is its low injection efficiency, typically in the 10
−6
range. This causes programming to be slow and to consume a large amount of power. A separate problem associated with dual bit SONOS structures is that a portion of the charge will spread into the area between the source charge storage region
11
and the drain charge storage region
13
during each program/erase cycle. The spread charge affects the threshold voltage during the read cycle. The charge that accumulates between the source charge storage region
11
and the drain charge storage region
13
is difficult to remove utilizing the hot hole injection erase mechanism. The problem is further compounded by the continued decrease in the size of the semiconductor devices, which calls for nitride layers with less area separating the two charge storage regions
11
and
13
. A need exists for a process of fabricating a dual bit memory cell structure that does not suffer the disadvantages discussed above.
SUMMARY OF THE INVENTION
A first aspect of the present invention is to provide dual bit dielectric memory cell which stores a charge within a charge trapping layer that is isolated from a substrate by a tunnel dielectric and isolated from a control gate by a top dielectric layer. The substrate comprises a source region, a drain region, and a channel region positioned between the source region and the drain region. A multi level charge trapping dielectric is positioned on the surface of the substrate and a control gate is positioned on the surface of the multilevel charge trapping dielectric.
The multilevel charge trapping dielectric includes the tunnel dielectric layer adjacent to the substrate, the charge trapping layer, and the top dielectric layer. The tunnel dielectric layer includes a central region that is laterally positioned between a source lateral region and a drain lateral region. The thickness of the tunnel dielectric layer in the central region has a thickness that is greater than the thickness of the tunnel dielectric layer in each of the source lateral region and the drain lateral region.
The thickness of the tunnel dielectric layer in each of the source lateral region and the drain lateral region may be within a range of about 50 Å and 150 Å. The thickness of the tunnel dielectric layer in the central region may be within a range of about 70 Å (angstrom) and 200 Å in thickness. The charge trapping layer may have a thickness in the range from about 50 Å to 10 Å in thickness across the central region, the source lateral region, and the drain lateral region.
The charge trapping layer may be comprised of a nitride compound such as a material selected from the group consisting of Si
3
N
4
and SiO
x
N
4
. The charge trapping layer within the source lateral region may form a source charge trapping region and the length of the source lateral region may be within a range of about 300 Å to 500 Å. Similarly, the charge trapping layer within the drain lateral region may form a drain charge trapping region and the length of drain charge trapping region may be within a range of about 300 Å to 500 Å. The length of the central region may be within a range of about 70 Å to 200 Å.
A second aspect of the present invention is to provide a method of storing data in dual bit dielectric memory cell that includes a tunnel dielectric layer having a tunnel layer with a thickness in a central region positioned between a source lateral region and a drain lateral region that is greater than a thickness in each of the source latera

Affiliated with

Also associated with

Rating

High density dual bit flash memory cell with non planar... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High density dual bit flash memory cell with non planar..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density dual bit flash memory cell with non planar... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3253264