Programmable logic array embedded in mask-programmed ASIC

Details Programmable logic array embedded in mask-programmed ASIC Programmable logic array embedded in mask-programmed ASIC

2001-06-08

2004-07-27

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06769109

ABSTRACT:

FIELD OF INVENTION
This invention generally relates to Application Specific Integrated Circuits (ASICs), and particularly to Programmable Logic Arrays (PLAs) incorporated into non-reprogrammable ASIC devices.
BACKGROUND
Application Specific Integrated Circuits (ASICs) have become widespread in the semiconductor industry. ASICs are generally integrated circuits that are customizable to implement a circuit specified by a design engineer or other user (a “user-defined” or “user-specified” circuit).
ASICs can be divided into two groups: (1) those that are “multi-time configurable” or “reconfigurable” (i.e., they can be programmed with data and reprogrammed) and (2) those that are only “one-time configurable” or “non-reconfigurable.” Multi-time configurable devices include Programmable Logic Devices (PLDs) and FPGAs. One-time configurable devices include some gate arrays and module-based arrays (MBAs). A general discussion of each technology will be useful.
Multi-time Configurable Devices
Generally, most PLDs are based on a PLA structure where a function is expressed in product terms and sum terms to be implemented. Each product term is generated by a gate that can be programmed to form the AND of any subset of the inputs and their complements. Subsets of the product terms can be summed in a set of programmable OR gates.
PLAs are constructed in the form of arrays, with the input lines being orthogonal to the product lines, as shown in the generalized circuit diagram of FIG.
1
.
FIG. 1
shows one type of PLA known as a PAL. In
FIG. 1
, PAL
100
includes inputs
106
, A, B, and C, where each input and its complement is input into programmable AND array
102
on lines
104
. Product term lines
110
are formed orthogonal to lines
104
. When the intersection between the input term and a product term line is programmed, then “AND terms” or “product terms”
108
are formed. The product terms
108
are then fed into OR gates
112
, forming “sum terms”
114
.
Product-terms are often implemented with a wired-OR mechanism, where multiple programmable transistors
116
are connected to the product-term line
110
and a pull-up
118
is used, as shown in the generalized circuit diagram of FIG.
2
. Although the pull-up
118
is shown as a resistor in
FIG. 2
, frequently a passive pull-up is implemented with a biased P-channel transistor instead.
A second type of PLA structure (sometimes referred to as a “Full PLA”) is shown in
FIG. 3
, having both a programmable AND array
102
and a programmable OR array
111
. In other words, both product terms and sum terms can be programmed using the device of FIG.
3
. Relative to the device of
FIG. 1
, the device of
FIG. 3
sacrifices some speed, but has greater programming flexibility and is better for implementing state machines. As well, unlike the
FIG. 1
device, in the
FIG. 3
device, product terms can be shared among all OR terms. Thus, the device of
FIG. 3
can implement any set of combinational logic limited only by the number of inputs, outputs, and product terms.
Flexibility of PLA structures, including those of
FIGS. 1 and 3
, can be further enhanced by adding flip-flops to one or more of the outputs to create general-purpose sequential circuits, often referred to as “sequencers.” A generalized block diagram of such a device is shown in FIG.
4
. In
FIG. 4
, the sum terms
114
output from the OR array
111
can feed directly to output pins
506
or to inputs of a flip-flop
508
. The flip-flop outputs can be fed back either to the AND array
102
or directly to output pins
506
. Product terms
108
can also be fed back into the AND array, often through an inverter
510
to create “expander” terms (such feedback often creates what is known as a NAND-NAND array or a NOR-NOR array). Not all sequencers have all of these options available. Nonetheless, such options are ideal for state machines.
Each of the conventional PLA structures described in
FIGS. 1-4
is usually a discrete device and is programmable and reprogrammable by the user either using a specialized programming device or in-system as is understood in the art. As should be understood in the art from
FIGS. 1-4
, there are numerous types of PLAs available and those described are exemplary only.
One-time Configurable Devices
The second category of ASIC mentioned is a one-time configurable ASIC, frequently gate arrays, MBAs, or standard cells. Typically, these one-time configurable devices are configured (or customized) by “mask-programming”—i.e., these devices are customized once using various mask and etch steps to form interconnections dictated by a user-defined circuit. Once configured, these mask-programmed devices are not reconfigurable.
An example MBA is shown in the generalized block diagram of
FIG. 5
, and is composed of an array
702
of function blocks
704
. Each function block
704
in an MBA usually includes a predefined circuit that is often identical in all function blocks. To customize the device, mask-programming techniques are used to interconnect the function blocks in a manner that creates a user-defined circuit. In other words, to configure the device, mask and etch techniques are used to form the conductors that interconnect the blocks
704
and/or interconnect active devices within the blocks
704
.
Gate arrays are known in the art and are similar in many respects to MBAs, except they are frequently composed of a “sea of gates”—prefabricated transistors that are (for the most part) unconnected to one another. These gate arrays are also configured using mask and etch techniques to interconnect the active devices and thereby form a user-defined circuit.
More specifically, as shown in
FIG. 6
, each MBA (or standard cell or gate array) is formed from many layers that usually include an active layer
810
(where active devices such as transistors are formed) and several metal layers (M
1
-M
4
)
820
,
830
,
840
, and
850
separated by insulation layers
815
,
825
,
835
,
845
. Frequently, an MBA device will be prefabricated up through a particular metal layer, say M
2
. Then customizing will be done in metal layers above, say M
3
and M
4
. Although four metal layers are shown, MBAs can contain more or fewer metal layers, and four is used as exemplary only. As well, customization can be done using any number of metal layers.
Another type of mask-programmed device is a “standard cell.” A standard cell is similar to an MBA, but instead of predefined function blocks, it includes custom cells that are optimized for performing a respective designated function. In other words, compared to MBA function blocks, the custom cells of a standard cell device have adjusted transistor size and placement and have eliminated extraneous devices. Thus, standard cells are customized in all the layers shown in
FIG. 6
, including active layers
810
. Both MBAs and standard cells, however, often use libraries to store available potential logic functions that can be implemented by function blocks (in the case of MBAs) or a custom cell (in the case of standard cells) for easier configuration. Gate arrays can also utilize similar libraries.
Once the customizing metal layers have been designed and implemented, the mask-programmed device (e.g., MBA or standard cell) is said to have been configured—but it cannot be reconfigured. As a result, designers of mask-programmed ASICs typically implement high-speed logic functions, including state machines and control logic, with conventional non-reconfigurable ASIC gates. Still, in many instances, when a mask-programmed device is configured, many parts of the implemented circuit are not fully verified. Moreover, during the development process, changes often need to occur in certain parts of the circuit, such as the control logic. Therefore, frequently portions of the circuit that are to be reconfigurable or may need to be changed are typically separately implemented in a separate PLD device. Thus, it is desirable to maintain some level of reconfigurability in at least part of the circuit, thereby minimizing the use of multiple ICs

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