Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2002-09-03
2004-09-14
Phung, Anh (Department: 2824)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S211000, C365S242000
Reexamination Certificate
active
06791865
ABSTRACT:
TECHNICAL FIELD
The technical field relates to memory devices capable of calibrating write currents in order to compensate for temperature variations.
BACKGROUND
Magnetic Random Access Memory (MRAM) is a proposed type of non-volatile memory. MRAM devices allow faster data access than conventional storage devices such as hard drives.
FIG. 1
illustrates a conventional MRAM memory array
10
having resistive memory cells
12
located at cross points of row conductors
14
and column conductors
16
. Each memory cell
12
is capable of storing the binary states of “1” and “0.”
FIG. 2
illustrates a conventional MRAM memory cell
12
. The memory cell
12
includes a pinned layer
24
and a free layer
18
. The pinned layer
24
has a magnetization of fixed orientation, illustrated by the arrow
26
. The magnetization of the free layer
18
, illustrated by the bi-directional arrow
28
, can be oriented in either of two directions along an “easy axis” of the free layer
18
. The magnetizations of the free layer
18
and the pinned layer
24
can be either “parallel” or “antiparallel” to one another. The two orientations correspond to the binary states of “1” and “0,” respectively. The free layer
18
and the pinned layer
24
are separated by an insulating tunnel barrier layer
20
. The insulating tunnel barrier layer
20
allows quantum mechanical tunneling to occur between the free layer
18
and the pinned layer
24
. The tunneling is electron spin dependent, making the resistance of the memory cell
12
a function of the relative orientations of the magnetizations of the free layer
18
and the pinned layer
24
.
Each memory cell
12
in the memory array
10
can have its binary state changed by a write operation. Write currents Ix and Iy supplied to the row conductor
14
and the column conductor
16
crossing at a selected memory cell
12
switch the magnetization of the free layer
18
between parallel and antiparallel with the pinned layer
24
. The current Iy passing through the column conductor
16
results in the magnetic field Hx, and the current Ix passing through the row conductor
14
results in the magnetic field Hy. The fields Hx and Hy combine to switch the magnetic orientation of the memory cell
12
from parallel-to-antiparallel. A current −Iy is applied along with the current Ix to switch the memory cell
12
back to parallel.
In order to switch the state of the memory cell
12
from parallel-to-antiparallel, and vice versa, the combined field resulting from +/−Hx and Hy exceeds a critical switching field Hc of the memory cell
12
. If Hx and Hy are too small, they will not switch the orientation of the selected memory cell
12
. If either Hx or Hy is too large, memory cells
12
on the row conductor
14
or the column conductor
16
of the selected memory cell
12
may be switched by the action of either Hx or Hy acting alone. Memory cells
12
subjected to either Hx or Hy alone are referred to as “half-selected” memory cells.
A problem may arise in MRAM arrays because the operational modes of an MRAM array and operating ambient temperature changes may cause the temperature of the MRAM array to vary, which would cause the coercivities of the memory cells to change. A change in coercivity of the memory cells changes the critical switching field Hc, which in turn changes the fields Hx and Hy required to switch the state of the cells. Temperature-dependent changes in critical switching field Hc increase the likelihood that an entire row or column of half-selected memory cells will be programmed due to the action of Ix or Iy alone, or, the likelihood that the write currents Ix and Iy acting together will be insufficient to switch a selected memory cell.
SUMMARY
According to a first embodiment, a memory device comprises a substrate, an array of memory cells disposed over the substrate, a plurality of first conductors, a plurality of second conductors, wherein the first conductors cross the second conductors at the memory cells, a first current source selectively coupled to the first conductors and capable of providing a first write current to selected first conductors, a second current source selectively coupled to the second conductors and capable of providing a second write current to selected second conductors, a controller for controlling the application of the first and second write currents to the array of memory cells, and a temperature sensor disposed in the memory device. The temperature sensor senses a temperature of the memory device, and data from the temperature sensor are used to update the first and second write currents according to the sensed temperature.
According to a second embodiment, a method of calibrating a memory device comprises detecting a temperature of the memory device, determining whether the temperature of the memory device has changed by a threshold value, and updating at least one write current value if the temperature of the memory device changes by the threshold value.
According to a third embodiment, a method of filling a table with write current values for use in a memory device comprises applying a first write current and a second write current to conductors crossing at a reference memory cell when the memory array is at a temperature, detecting a state of the reference memory cell, increasing the first write current and the second write current if the state of the reference memory cell does not change, repeating the above steps until the state of the reference memory cell changes from a first state to a second state, and storing the first write current value and the second write current value that cause the state of the reference memory cell to change, wherein the first and second write current values are associated with the temperature.
Other aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying figures.
REFERENCES:
patent: 5650958 (1997-07-01), Gallagher et al.
patent: 5793697 (1998-08-01), Scheuerlein
patent: 5943286 (1999-08-01), Orita
patent: 6055178 (2000-04-01), Naji
patent: 6111781 (2000-08-01), Naji
patent: 6128239 (2000-10-01), Perner
patent: 6185143 (2001-02-01), Perner et al.
patent: 6188615 (2001-02-01), Perner et al.
patent: 6259644 (2001-07-01), Tran et al.
patent: 6317376 (2001-11-01), Tran et al.
patent: 6369712 (2002-04-01), Letkomiller et al.
patent: 6385082 (2002-05-01), Abraham et al.
patent: 6476716 (2002-11-01), Ledlow
patent: 6608790 (2003-08-01), Tran et al.
Yaoi, T., et al., “Dependence of Magnetoresistance on Temperature and Applied Voltage in a 82Ni-Fe/Al-Al2 03/Co tunneling Junction”, Journal of Magnetism and Magnetic Materials 126, North-Holland, (1993) p.p. 430-432.
Bhattacharyya Manoj K.
Tran Lung T.
Hewlett--Packard Development Company, L.P.
Nguyen Tuan T.
Phung Anh
LandOfFree
Memory device capable of calibration and calibration methods... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory device capable of calibration and calibration methods..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device capable of calibration and calibration methods... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3252607