Semiconductor device with crenellated channel

Details Semiconductor device with crenellated channel Semiconductor device with crenellated channel

2002-12-12

2004-03-16

Nguyen, Cuong (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S338000, C257S357000, C257S408000

Reexamination Certificate

active

06707113

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device of the metal-oxide-semiconductor type, more particularly to a semiconductor device with improved resistance to defects and particle contamination.
2. Description of the Related Art
Metal-oxide-semiconductor (MOS) devices are fabricated in large quantities from wafers of crystalline silicon. Although every effort is made to keep the wafers clean during the fabrication process, it is impossible to eliminate all contamination. Typically, the fabrication facility and process are designed to eliminate contaminating particles above a specified maximum size, but wafer surfaces may still be contaminated by smaller particles. The contaminating particles may include, for example, atmospheric dust particles, particles of oxide or other dielectric materials that become detached from the walls of chemical vapor deposition apparatus, and particles of metal or other conductive materials that become similarly detached.
Aside from particle contamination, wafer surfaces may have defects in their crystalline structure. Such defects may be created by stress arising during local oxidation of the silicon surface, for example.
Particles and defects cause various problems in MOS devices. In a MOS memory device of the type in which each memory cell is a field-effect transistor with a floating gate, a particle or defect can alter the capacitive coupling ratio between the floating gate and the source, drain, or substrate of the transistor. As a result, when the memory cell is programmed or erased by transferring electrons into or out of the floating gate, the necessary programming time or erasing time is altered.
When a floating-gate memory device is programmed or erased, a plurality of memory cells may be programmed or erased simultaneously by a series of high-voltage pulses. After each pulse, the transistor threshold voltage of the memory cells is measured. High-voltage pulses are applied repeatedly until a satisfactory threshold voltage is obtained for at least one of the memory cells, or for all of the memory cells, depending on the memory architecture and the type of operation (programming or erasing) . If one of the memory cells has a defect that makes it reach the desired threshold voltage in an abnormally short or abnormally long time, then that memory cell may be left in an over-programmed, under-programmed, over-erased, or under-erased state. Alternatively, that memory cell may be left in the correct state while other memory cells are over-programmed, under-programmed, over-erased, or under-erased. The result in either case is that tests are failed and the device has to be repaired or discarded.
Other problems include leakage of data through conductive defects in the oxide films that insulate the floating gates from the substrate, and reduction of the current-driving capability of transistors if a particle or defect reduces the transistor's channel width.
SUMMARY OF THE INVENTION
An object of the present invention is to mitigate the effect of particle contamination and defects on a MOS device.
A MOS device according to the present invention has a transistor with a source and drain of a first conductive type, and a channel region of a second conductive type disposed between the source and the drain. The source, drain, and channel region are disposed in an active region surrounded by a field region providing electrical isolation. The channel region and field region have a crenellated common boundary. The crenellations are preferably at least as large as the specified maximum size of contaminating particles permitted in the process by which the MOS device is fabricated.
The crenellations may be formed by exploiting the tendency of polysilicon-buffered local oxidation of silicon to follow contours defined by polysilicon grain boundaries. The process conditions should then be selected to produce large polysilicon grains. Alternatively the crenellations may be formed by use of a crenellated mask pattern.
The crenellations reduce the effect of a contaminating particle or defect disposed at the boundary between the channel region and field region. Since the boundary was irregular to begin with, the further irregularity introduced by the particle or defect does not greatly alter the effective channel width or change the electrical characteristics of the transistor.
For a MOS memory device with floating gates, the invention improves the manufacturing yield by reducing the probability that a particle or defect will significantly alter the programming time or erasing time of a memory cell.


REFERENCES:
patent: 6407423 (2002-06-01), Okumoto

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