Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-08-30
2004-04-13
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S226000
Reexamination Certificate
active
06721210
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory circuits and, more particularly, to an improved voltage boosting circuit for a wordline driver for a dynamic random access memory.
2. Prior Art
The power consumed in a semiconductor memory varies as the square of the supply voltage. Therefore, to conserve power, it is advantageous to operate memory circuits at lower supply voltages. In certain low-power memory circuit designs, the operating supply voltage may actually be chosen to be even lower than the operating supply voltage that is targeted for a particular process technology. For example, in a 0.18 micron dynamic random access memory DRAM process technology, voltages lower than 1.8 volts are considered to be low. In this case, DRAMs would require a boosted wordline voltage to operate properly.
Prior boost circuits provide boost capacitors in series with the gate terminal and the drain terminal of a pass transistor that drive a DRAM wordline. Some of these prior art boost circuits do not operate efficiently. FIG. 4 of U.S. Pat. No. 5,579,276 shows two capacitors, one in series with the gate of a pass transistor and the other in series with the drain of the pass transistor. This patent does not show any pre-charge circuit nor does it describe any circuit for precharging the capacitor A separate VCC voltage supply is required for the circuits that drive the boost capacitors.
Consequently, a need exists for a technique that efficiently generates a required boosted voltage for an SRAM when the operating voltage of the circuits is low and without the need for a separate voltage supply for the drivers of boost capacitors.
SUMMARY OF THE INVENTION
The present invention provides a PMOS pre-charge circuit for precharging a node to be boosted with the substrate of the PMOS precharging device connected to the same boosted node. Cutoff is provided for the precharging operation using an associated gate that turns off the PMOS precharging device when a node is boosted.
The gate terminal of the output pass transistor is boosted to a higher voltage by a circuit, which uses two boost capacitors. The higher voltage on the gate causes the boost voltage to be efficiently driven to the output node of the output pass transistor. In a further embodiment of the invention, the gate circuit of the output pass transistor is boosted to a higher 3 VCC voltage by a circuit which uses a pre-boost capacitor and a boost capacitor such that the higher voltage on the gate causes the drain boost voltage to be efficiently driven to the output terminal.
One embodiment of the present invention provides an improved voltage boosting circuit that boosts the output voltage of an NMOS pass transistor that functions as a wordline driver for a DRAM. The boosting circuit operates entirely from a single, common VCC voltage supply and has a gate input terminal to which is connected a gate boost capacitor and a PMOS precharge circuit. A drain terminal of the NMOS pass transistor is connected a drain boost capacitor and to a drain precharge circuit. A source output terminal of the NMOS pass transistor provides a boosted output voltage vh for a wordline of the DRAM.
The gate boost capacitor has a first terminal connected to the gate input terminal of the NMOS pass transistor and has a second terminal. A gate precharge circuit is connected to the gate input terminal of the NMOS pass transistor for precharging the first terminal of the gate boost capacitor from the common VCC voltage supply. The gate precharge circuit has a PMOS gate precharge transistor that has its source terminal connected to the common VCC voltage supply and that has a drain terminal and a substrate terminal connected together in common to the first terminal of the gate boost capacitor.
Means are provided for connecting the second terminal of the gate boost capacitor to a common ground while the gate precharge circuit precharges the first terminal of the gate boost capacitor from the common VCC voltage supply to provide a precharged gate boost capacitor. Means are also provided for connecting the second terminal of the precharged gate boost capacitor to the common VCC voltage level to thereby boost the precharged gate input terminal voltage to 2 VCC.
The drain boost capacitor has a first terminal connected to the drain input terminal of the NMOS pass transistor and has a second terminal. A drain precharge circuit is connected to the drain terminal of the NMOS pass transistor for precharging the drain terminal of the NMOS pass transistor with the common VCC voltage supply. The drain precharge circuit has a PMOS drain precharge transistor that has its source terminal connected to the common VCC voltage supply and that has its drain terminal and a substrate terminal connected together in common to the drain terminal of the NMOS pass transistor to precharge the drain terminal of the NMOS pass transistor to VCC.
Means are provided for connecting the second terminal of the drain boost capacitor to a common ground, while the drain precharge circuit precharges the first terminal of the drain boost capacitor from the common VCC voltage supply to provide a precharge drain boost capacitor. Means are also provided for connecting the second terminal of the drain boost capacitor to the common VCC voltage level to thereby boost the precharged drain terminal voltage to 2 VCC.
The voltage boosting circuit provides a boosted output voltage for a wordline of the DRAM at a level of 2 VCC minus the threshold voltage for the NMOS pass transistor.
The means for connecting the second terminal of the gate boost capacitor to the common ground and the means for connecting the second terminal of the precharge gate boost capacitor to the common VCC voltage include a CMOS gate circuit having an input terminal and having an output terminal that is connected through a PMOS pullup transistor to the common VCC voltage to thereby boost the gate voltage of the NMOS pass transistor to twice the VCC voltage or that is alternatively connected through an NMOS transistor to ground voltage during precharging of the gate boost capacitor.
Similarly, the means for connecting the second terminal of the drain boost capacitor to the common ground and the means for connecting the second terminal of the precharged drain boost capacitor to the common VCC voltage include a CMOS gate circuit having an input terminal and having an output terminal that is connected through a PMOS pullup transistor to the common VCC voltage to thereby boost the drain voltage of the NMOS pass transistor to twice the VCC voltage and that is alternatively connected through an NMOS pulldown transistor to ground voltage during precharging of the drain boost capacitor.
The PMOS gate precharge transistor has a gate terminal that is connected to an output terminal of a CMOS precharge inverter that has an NMOS pulldown transistor and a PMOS pullup transistor having a source terminal connected to the first terminal of the gate boost capacitor and to the gate terminal of the NMOS pass transistor. Similarly, the PMOS drain precharge transistor has a gate terminal that is connected to an output terminal of a CMOS precharge inverter that has an NMOS pulldown transistor and a PMOS pullup transistor having a source terminal connected to the first terminal of the drain boost capacitor and to the drain terminal of the NMOS pass transistor.
A logic circuit is provided that receives a high-voltage enable signal avhe and that provides control signals for activating the gate precharge circuit and the drain precharge circuit or alternatively for boosting the voltage on the gate and drain terminals of the NMOS pass transistor to provide a boosted output voltage vh for a wordline of a DRAM.
Another embodiment of the invention is similar to the first embodiment and further includes a gate preboost capacitor having a first terminal connected to a gate preboost terminal and having a second terminal. A gate preboost precharge circuit is connected to the gate preboost terminal for precharging the first ter
Lazar Paul S.
Oh Seung Cheol
King Patrick T.
Mai Son
Nanoamp Solutions Inc.
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