Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-01-27
2004-07-13
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S295000
Reexamination Certificate
active
06762446
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to integrated circuits and in particular to storage devices whose structure comprises a dielectric layer of capacitive coupling having ferroelectric features and/or a high dielectric constant, both in the case that the storage device employs the features of residual polarization of the ferroelectric oxide or the capacitive coupling through the dielectric oxide for storing information in the form of electric charge.
Ferroelectric and particularly dielectric compounds based on mixed oxides or equivalent compounds with ferroelectric features are materials used in different fields and particularly in the manufacture of integrated structures on a semiconductor or dielectric substrate. Piezoelectric filters, ultrasonic transducers which employ the piezoelectric features, infrared transducers, optical sensors employing features of pyroelectricity, optical modulation devices, and optical diaphragms based on the employment of electro-optical features are some applications of these materials.
The possibility of manufacturing extremely thin dielectric films of materials having ferroelectric features has favored the development of nonvolatile storage devices with ferroelectric capacitors, which employ the stability in time of the residual polarization of the thin layer of ferroelectric material of the capacitor. These devices (storage cells) have been developed by virtue of their potential to be manufactured in extremely compact size, so as to increase the storage capacity and the level of integration of the whole integrated device or their marked ability to preserve the information even in particularly hard conditions.
Ferroelectric dielectrics which are commonly used in the manufacturing processes of integrated devices are lead zirconate titanates, PbZr
(1-x)
Ti
(x)
O
3
, commonly known with the acronym PZT, bismuth and strontium tantalate or Sr
2
Bi
2
Ta
2
O
9
, commonly known with the acronym SBT or YI, and the lanthanum and bismuth titanates, commonly known with the acronym BLT. These are among the most used materials for manufacturing the so-called FeRAM storage devices.
Another similar dielectric material (also with ferroelectric features) used as a dielectric layer, in particular as dielectric interpoly of capacitive coupling between a control gate structure (wordline) and the floating gate of the cell in DRAM cell structures, is barium and strontium titanate, Ba
(x)
Sr
(1-x)
TiO
3
, also known with the acronym BST.
The materials preferably used for exploiting the ferroelectric features thereof in FeRAM are the above mentioned PZT and also the SBT or the BLT, whereas the BST is most frequently used in the DRAMs by virtue of an increased possibility of depositing extremely thin films thereof, having a high dielectric constant, free from defects.
The techniques of deposition of the layers of dielectric compounds with ferroelectric features can be various, such as by “sputtering”, or by chemical deposition from the vapor phase (CVD) wherein a decomposable compound, commonly an organometallic compound of precursor metals, is deposited from the vapor phase on a suitable substrate.
Another method of formation of these layers is the so-called “sol-gel” method, wherein a solution of precursor compounds is used in order to form a film on substrate, commonly by thermal decomposition of several applications of sol-gel. There is also a method based on the creation of a “mist” of ionized drops of a solution of a metallo-organic precursor compound, which are deposited on the wafers. Once the solvent is evaporated, the metallo-organic compound is decomposed at high temperature in a strongly oxidizing environment, so as to form a film of composite oxide. This technique is known in the literature as “Liquid Source Misted Chemical Deposition” or briefly LSMCD. Other methods of preparation are known in the literature.
Leaving out of consideration the particular function of the thin-film capacitor of dielectric material with high dielectric constant, optionally also with marked ferroelectric features, and the relevant integrated structure to which it belongs, whether that of a FeRAM, of a DRAM or other, the formation of the thin-film capacitor in the course of a manufacturing process of a common semiconductor integrated device, for example in CMOS technology, entails a number of problems due to a precise risk of exposure of the thin layer, generally based on oxides, to hydrogen. As a matter of fact, in the common course of a manufacturing process of integrated devices, there are a number of operations where hydrogen is present that remains partly trapped or incorporated in the wafer during the manufacture, typically in the semiconductor silicon substrate.
For example in a CMOS process, the devices (transistors) defined in the active areas can be exposed to an annealing treatment in hydrogen atmosphere for neutralizing bonds which are left “dangling” in the semiconductor, in order to reduce problems of superficial charge at the interface between the semiconductor and the gate oxide. During this annealing treatment, hydrogen can remain trapped in the substrate, which thus becomes a source of hydrogen diffusion during the working life of the integrated device. Other sources of exposure to hydrogen can be identified in the so-called “back-end” steps of the process, during the formation of metallizing aluminum layers, the steps of formation of tungsten plugs for the contacts and formation of the IDL layers, wherein the process conditions are such that the presence of hydrogen is implicated.
Hydrogen can also be present during the sealing and encapsulating steps of the integrated device, in the case of ceramic “packaging.” Also, during the working life of the devices, a certain diffusion of hydrogen inside the device can take place.
The effects of degradation of a dielectric film, optionally with ferroelectric features, generally formed of an oxide or more frequently of mixed oxides or equivalent compounds, upon exposure to hydrogen are well-known and discussed in the literature. In particular, a hydrogen degradation of the ferroelectric film of an FeRAM causes a contraction of the hysteresis curve, thus reducing the separation between the logical values 1 and 0 on the ordinate axis, which effect can bring about a difficulty in the discrimination criteria in the reading step of the information stored in the ferroelectric film capacitor. In the case of a DRAM, the degradation of the thin dielectric film of interpoly capacitive coupling determines a loss of electric charge stored in the floating gate through the wordline.
The suggestions made until now in order to overcome this critical aspect of the dielectric and ferroelectric materials having a high dielectric constant against a hardly avoidable hydrogen exposure have been several.
European published patent application EP-A-0 605 980 discloses a growth PECVD technique of a Si
3
N
4
and SiON layer having a low hydrogen content, as an inter-dielectric state of an FeRAM device, using TEOS (Si(OC
2
H
5
)
4
) and N
2
, instead of the common mixture of SiH
4
/NH
3
/N
2
.
U.S. Pat. No. 5,523,595 discloses the sputtering of a TiN or TiON layer on the FeRAM device using a PZT deposited via sol-gel, with functions of a barrier-layer against hydrogen and humidity.
U.S. Pat. No. 5,481,490 discloses the deposition of a thin layer of nitride of aluminum, silicon or titanium on the ferroelectric capacitor, in order to prevent the degradation of the ferroelectric film of the capacitor during the annealing treatments which are foreseen in the manufacturing process of the device, during which the gases H
2
and N
2
are used.
U.S. Pat. No. 5,591,663 discloses a particular sequence of a manufacturing process of an FeRAM device using conventional materials, which avoids the hydrogen degradation during the annealing treatment.
European published patent application EP-A-0 837 505 discloses a structure comprising a ferroelectric capacitor, wherein a second layer of ferroelectric material PZT is deposited on
Amiotti Marco
Boffito Claudio
Jung Jae Hak
Akin Gump Strauss Hauer & Feld L.L.P.
Ngo Ngan V.
Saes Getters S.p.A.
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