Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2003-01-17
2004-05-11
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S143000, C711S144000, C711S145000, C711S156000, C711S169000, C711S140000
Reexamination Certificate
active
06735675
ABSTRACT:
BACKGROUND
The present invention relates to an apparatus and method for an improved system of cache coherency in a multiple agent system.
In the electronic arts, a processing system may include a plurality of agents that perform coordinated computing tasks. The agents often share one or more main memory units designed to store addressable data for the use of all agents. The agents communicate with the main memory unit and each other over a communications bus during bus transactions. A typical system is shown in FIG.
1
.
FIG. 1
illustrates a plurality of N agents
10
,
20
,
30
,
40
in communication with each other over an external communications bus
50
. Data is exchanged among the agents
10
,
20
,
30
and the main memory unit
40
in a bus transaction. “Agents” include processors, memory units, and devices that may communicate over the communications bus
50
.
In order to improve performance, an agent may include a plurality of tiered internal caches that store and alter data on a temporary basis. In such multiple agent systems, several agents may operate on data from a single address at the same time. Multiple copies of data from a single memory address may be stored in multiple agents. Oftentimes when a first agent must operate on data at an address, a second agent may store a copy of the data that is more current in its internal cache than the copy resident in the main memory unit
40
. In order to maintain “cache coherency,” the first agent should read the data from the second agent rather than from the main memory unit
40
. Without a means to coordinate among agents, an agent may perform a data operation on a copy of data that is stale.
Along with each unit of data, an internal cache may store additional information, which may include the data's address in the main memory unit
50
, the length of the data unit, and/or an indicator as to whether the data has been modified by the agent since being retrieved from main memory. This indicator—known as the “state” of the data—may reflect that the data has been modified or unmodified since being retrieved from main memory. Each agent may include cache coherency circuitry that ensures that data in a modified state is eventually returned to the main memory unit
40
via the communications bus
50
.
In some agents, modified data may be returned to main memory as part of an “explicit writeback” transaction or as part of an “implicit writeback.” In an explicit writeback, an agent generates a bus transaction to write the modified data to external memory in order to make room in the cache for newly requested data. That is, the agent (e.g.,
10
in
FIG. 1
) acquires ownership of the communications bus
50
and drives the modified data on the communications bus
50
. The external memory (e.g., agent
40
in
FIG. 1
) retrieves the data from the communications bus
50
and stores it according to conventional techniques.
By contrast, an implicit writeback typically occurs as part of a transaction initiated by another agent. Consider an example where agent
10
stores a copy of data in modified state; the copy in agent
10
is more current than a copy stored in the main memory unit
40
. If another agent
20
posts a request on the communications bus
50
and requests the data, an implicit writeback would cause agent
10
to provide the requested data to agent
20
rather than the main memory unit
40
.
In an implicit writeback, when agent
20
posts the request each of the other non-requesting agents performs an internal check to determine whether it possesses a modified copy of the data at the requested address in its internal cache system. If a non-requesting agent (agent
10
in the example) does have a modified of the requested data in its internal cache system it so indicates in a cache coherency signal of the transaction. The agent
10
drives the modified data on the external communications bus
50
. The requesting agent
20
and the main memory unit
40
may read the data from the communications bus
50
.
In almost all circumstances, explicit writebacks and implicit writebacks can proceed concurrently in a multiple agent system without violating cache coherency. Because explicit writebacks and implicit writebacks are not acted upon immediately, but are often placed in a pipeline of operations to be preformed at a later time by an agent or a communications bus, a problem in cache coherency can occur in the boundary condition when an agent initiates an implicit writeback for data at a particular address while the agent is in the process of performing an explicit writeback of data from the same address. In this situation, it is possible for the agent to report newly updated data to the main memory unit via the implicit writeback before agent processes the external writeback for the same address. Cache coherency would be violated when the agent then processes the explicit writeback, because the explicit writeback will update memory with a copy of data from a particular address that is not the most current copy.
In the prior art, the solution to this problem was to temporarily halt all explicit writebacks during the time an implicit writeback was being processed. This suspension of all explicit writebacks resulted in a substantial performance loss, given that the probability that an implicit writeback and an explicit writeback involved data from the same address, and thus that cache coherency would actually be compromised, was quite small.
Accordingly, there is a need in the art for a system and method that allows the performance of explicit writebacks to continue during the processing of implicit writebacks while still maintaining cache coherency during the boundary condition where an agent initiates an implicit writeback for data at a particular address while the agent is in the process of performing an explicit writeback of data from the same address.
SUMMARY
Embodiments of the present invention provide for a transaction management method for a processing agent in which the agent receives a request for data identified by an address. The agent then determines whether it has in store a pending write transaction to the address and, if so, sets a transaction length associated with the pending write transaction to zero.
REFERENCES:
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5664150 (1997-09-01), Isaac et al.
patent: 5737759 (1998-04-01), Merchant
patent: 5905876 (1999-05-01), Pawlowski et al.
patent: 6145062 (2000-11-01), Chittor et al.
patent: 6434677 (2002-08-01), Breuder et al.
patent: 2002/0156982 (2002-10-01), Breuder et al.
Bachand Derek T.
Breuder Paul D.
Hill David Lawrence
Prudvi Chinna
Anderson Matthew D.
Kenyon & Kenyon
Kim Matthew
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