Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output expansion
Reexamination Certificate
2000-05-22
2004-03-30
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output expansion
C710S005000, C710S007000, C710S036000, C711S167000
Reexamination Certificate
active
06714993
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to external memory interfaces, and more particularly to a method and apparatus for efficiently interfacing a peripheral memory, such as a slow flash device, with a processor, such as a fast digital signal processor.
2. Description of the Related Art
The ever increasing clock speeds of microprocessors have garnered much attention lately. Generally speaking, faster microprocessors mean faster, more powerful personal computers. The same is true for any electronic or computing device that relies on any of the several types of processors. These “other” types of processors include, for instance, digital signal processors (“DSPs”) and micro-controllers. Just as microprocessors have steadily increased in power and speed, so have other types of processors. The power and speed of all manner of electronic and computing equipment consequently continues to increase dramatically.
However, processor clock speed is not the only, or even the determining factor in power and efficiency of a system as a whole. Performance of even the fastest, most powerful processor can be radically affected by other system design features. For instance, processors must communicate with other system components over “buses.” The amount of information that may be transmitted over a bus in a given time period is its “bandwidth,” a characteristic generally independent of the processor's clock speed. Thus, a fast processor's performance may be limited by a slow bus, since the bus can only transmit a limited amount of data no matter how fast the processor can actually communicate it to or from the bus.
Performance may also be compromised by interfacing a fast processor with a slow peripheral device. Processors typically interact with the outside world through peripheral devices. For instance, a processor in a personal computer may receive input from a user through a keyboard or a mouse, display information over a monitor, or output information to a printer. The keyboard, mouse, monitor, and printer are all “peripheral” devices. The processor's performance may be degraded in this circumstance by a number of factors, including slow response time by the peripheral or complicated protocols that must be followed to ensure an accurate transmission between the processor and the peripheral.
In fact, utilization of peripheral devices is a common inhibitor of processor performance and can frequently be traced to slow response. The typical approach employed by most processors in this circumstance is to initiate the access (i.e., a read from or a write to) and then wait for the peripheral device to become ready for the access. More technically, the processor enters a “wait state,” in which its operations typically cease until the peripheral device is ready. These wait states invariably are longer than it takes the processor to execute most instructions, or even a series of instructions. Thus, precious instruction cycles in which the processor might be performing useful tasks are wasted waiting on the peripheral device. It takes only a few accesses to a peripheral device in these circumstance to degrade the performance of a system including a fast, powerful processor.
One attempt to meet some of these challenges is called “system on a chip”, or “SOC.” This approach tries to combine a variety of functions typically found in separate parts of a computing system onto a single chip. Several drawbacks associated with buses and access time can be mitigated. However, it has exacerbated at least one problem: the object of most SOC integrated circuit (“IC”) designs is to create a general purpose programmable system that leaves future modifications and enhancements to firm-ware modification alone to enhance the life cycle of the IC. Due to ever-changing timing specifications of external peripherals, this is hard to accomplish. Modifications or enhancements to the IC other than software modifications are difficult or expensive to implement. This becomes more significant over the life of the IC as peripheral devices evolve to employ new or otherwise different protocols.
The present invention is directed to resolving one or all of the problems mentioned above.
SUMMARY OF THE INVENTION
The invention, in its many aspects and variations, includes a method for accessing a peripheral memory from a processor. The method comprises first initiating the access. Information is then written from the processor to an operational register in a processor memory to enable the peripheral memory. The processor then processes parallel instructions for a predetermined time during which the access occurs. When the access is over, the processor reads the operational register to disable the peripheral memory. In other aspects, the invention includes an apparatus programmed to perform this method and a program storage medium encoded with instructions that, when executed by a computer, perform the method.
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Gaffin Jeffrey
Legerity Inc.
Sorrell Eron
Williams Morgan & Amerson
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