Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-11-04
2004-03-16
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S185050, C365S185230, C365S230060
Reexamination Certificate
active
06707700
ABSTRACT:
This application claims the benefit of Korean Patent Application No. P2001-68652 filed in Korea on Nov. 5, 2001, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a nonvolatile memory device and a driving method thereof enabling to reduce a layout and provide an excellent sensing margin using current sensing even if a capacitance load of a main bitline is heavy.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory device, i.e. FRAM (ferroelectric random access memory), has a data processing speed similar to that of DRAM as well as enables to keep data in store when power is off, thereby attracting public attention as a next generation memory device.
FRAM is a memory device having a structure similar to that of DRAM, and uses ferroelectrics as a capacitor material so as to apply a ferroelectric characteristic of high remaining polarization thereto
Data fails to be erased owing to such a remaining polarization characteristic even if an electric field is removed.
FIG. 1
illustrates a graph of a hysteresis loop characteristic of general ferroelectrics.
Referring to
FIG. 1
, polarization induced by an electric field fails to be eliminated even if the electric field is removed, but maintains a predetermined quantity (d or a state) owing to remaining polarization (or spontaneous polarization).
A nonvolatile ferroelectric memory cell is a memory device using the d and a states as 1 and 0, respectively.
A nonvolatile ferroelectric memory according to a related art is explained in the following by referring to the attached drawings.
FIG. 2
illustrates a diagram of a unit cell of a general ferroelectric memory.
Referring to
FIG. 2
, a bitline B/L is formed in one direction, a wordline W/L is formed in a direction crossing with the bitline B/L, a plate line P/L is formed in the same direction of the wordline W/L so as to leave a predetermined interval from the wordline, a transistor T
1
is formed so that a gate and a source are connected to the word and bitlines, respectively, and a ferroelectric capacitor FC
1
is formed so that first and second terminals of the ferroelectric capacitor FC
1
are connected to a drain of the transistor T
1
and the plate line P/L, respectively.
Data input/output operation of such a nonvolatile ferroelectric memory device is explained as follows.
FIG. 3A
illustrates an operation timing diagram of a ferroelectric memory at write mode, and
FIG. 3B
illustrates an operation timing diagram of a ferroelectric memory at read mode.
First of all, in case of a write mode, a chip enable signal CSBpad applied from outside is activated high to low, and simultaneously, a write enable signal WEBpad is applied high to low. Thus, the write mode is initiated.
Subsequently, once address decoding starts at the write mode, a pulse applied to the corresponding wordline is shifted low to high so as to select a cell.
Hence, high and low signals for predetermined sections are successively applied to the corresponding plate line in a section that the wordline maintains the high state. And, in order to write a logic value “1” or “0” on the selected cell, a high of low signal synchronized with the write enable signal WEBpad is applied to the corresponding bitline.
Namely, if the signal applied to the plate line is low in the section that the signal applied to the wordline is high and that the high signal is applied to the bitline, the logic value “1” is recorded in the ferroelectric capacitor. If the signal applied to the plate line is high when the low signal is applied to the bitline, the logic value “0” is recorded in the ferroelectric capacitor.
Operation of reading data stored in the cell is explained as follows.
When the chip enable signal CSBpad is activated high to low externally, all the bitlines are equalized into a low voltage by an equalizing signal before the corresponding wordline is selected.
After each bitline is deactivated, the address is decoded. Then, the low signal at the corresponding wordline is shifted to the high signal by the decoded address so as to select the corresponding cell. The high signal is applied to the plate line of the selected cell, whereby a data Qs corresponding to the logic value “1” stored in the ferroelectric memory is destroyed.
If the logic value “0” is stored in the ferroelectric memory, a data Qns is not destroyed. The destroyed and non-destroyed data output values different from each other by the hysteresis loop principle, whereby a sense amplifier senses the logic value “1” or “0”.
Namely, in case that the data is destroyed, the state is changed from d to f like the hysteresis loop in FIG.
1
. And, in case that the data is not destroyed, the state is changed from a to f. Hence, when the sense amplifier is enabled after lapse of a time, amplification occurs so as to output the logic value “1” in case that the data is destroyed. And, when the data is not destroyed, amplification occurs to output the logic value “0”.
The original data should be restored after the sense amplifier has amplified the data. Hence, the plate line is deactivated “high” to “low” while the high signal is applied to the corresponding wordline.
Explained in the following is a nonvolatile ferroelectric memory having a hierarchical folded bitline structure according to a first method of the related art.
Referring to
FIG. 4A
, a nonvolatile ferroelectric memory mainly includes a top cell array block
10
and a bottom cell array block
11
. And, a sense amplifier
12
is arranged every two bitlines in the middle of the top and bottom cell array blocks
10
and
11
.
In this case, the bitline means a main bitline. Besides, a sub-bitline (not shown in
FIG. 4A
) is further includes so as to correspond to one main bitline.
Moreover, a switching control block (not shown in
FIG. 4A
) is further included so as to control a connection between the main bitline and sub-bitline as well as a voltage transferred to a ferroelectric capacitor of each cell.
Column switch blocks
13
and
14
are connected to both ends of each of the bitlines, respectively. And, data buses io<m>, . . . , and io<n> are connected to the column switch blocks
13
and
14
.
And, a main amplifier at one corner of the entire cell array block is connected to each of the data buses io<m>, . . . , and io<n> of the top and bottom cell array blocks
10
and
11
.
Each of the top and bottom cell array blocks
10
and
11
includes a plurality of sub-cell array blocks
15
_
0
~
15
_n and
16
_
0
~
16
_n.
And, reference cell array blocks
17
and
18
are included so as to correspond to the top and bottom cell array blocks
10
and
11
, respectively.
In this case, the reference cell array block
17
is constituted between the top cell array block
10
and the corresponding column switch blocks
13
.
And, the reference cell array block
18
is constituted between the bottom cell array block
11
and the corresponding column switch blocks
14
.
A nonvolatile ferroelectric memory having a hierarchical open bitline structure according to a second method of the related art, as shown in
FIG. 4B
, has the same constitution in
FIG. 4A
but differs from the first method only in that one sense amplifier
22
is connected to each main bitline and cells of each cell array block are formed at each of pairs of word and plate lines and a sub-bitline.
Unfortunately, the nonvolatile ferroelectric memory device according to the related art has the following problems or disadvantages.
First, it is difficult to reduce a layout since the sense amplifier is arranged at each cell array block.
Second, the cell data is processed by voltage sensing. Hence, a sensing margin is decreased when a capacitance load of the main bitline is large or the main bitline has a capacitance mismatch.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a nonvolatile ferroelectric memory device and a driving method thereof that substantially ob
Auduong Gene
Hynix Demiconductor Inc.
Morgan & Lewis & Bockius, LLP
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