Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-07-23
2004-09-14
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06792586
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to electronic circuits and more particularly to complex computer aided design layout and design rule verification of a design layout of, for example, an integrated circuit (IC) device or printed wiring board, in preparation for fabrication.
2. Description of the Related Art
Design of an electronic circuit, for example, an integrated circuit (IC), is a complicated and time consuming process.
FIG. 1
illustrates a typical design flow
100
of an integrated circuit device from conception through the generation of a fabrication ready design layout. Generally, design flow
100
commences with defining the design specifications or requirements, such as required functionality and timing, step
102
. The requirements of the design are implemented, for example, as a net-list or electronic circuit description, step
104
. The implementation can be performed by, for example, schematic capture (drawing the design with a computer aided design tool) or more typically, utilizing a high level description language such as VHDL, Verilog and the like. The implemented design is simulated to verify design accuracy, step
106
. Design implementation and simulation are iterative processes. For example, errors found by simulation are corrected by design implementation and re-simulated.
Once the design is verified for accuracy with simulation, a design layout of the design is created, step
108
. The design layout describes the detailed design geometries and the relative positioning of each design layer to be used in actual fabrication. The design layout is very tightly linked to overall circuit performance (area, speed and power dissipation) because the physical structure defined by the design layout determines, for example, the transconductances of the transistors, the parasitic capacitances and resistances, and the silicon area which is used to realize a certain function. The detailed design layout requires a very intensive and time-consuming design effort and is typically performed utilizing specialized computer aided design (CAD) or Electronic Design Automation (EDA) tools.
The design layout is checked against a set of design rules in a design rule check (DRC), step
110
. The created design layout must conform to a complex set of design rules in order, for example, to ensure a lower probability of fabrication defects. The design rules specify, for example, how far apart various layers must be, or how large or small various aspects of the layout must be for successful fabrication, given the tolerances and other limitations of the fabrication process. A design rule can be, for example, a minimum spacing amount between geometries and is typically closely associated to the technology, fabrication process and design characteristics. For example, different minimum spacing amounts between geometries can be specified for different sizes of geometries. DRC is a time-consuming iterative process that often requires manual manipulation and interaction by the designer. The designer performs design layout and DRC iteratively, reshaping and moving design geometries to correct all layout errors and achieve a DRC clean (violation free) design.
Circuit extraction is performed after the design layout is completed and error free, step
112
. The extracted circuit identifies individual transistors and interconnections, for example, on various layers, as well as the parasitic resistances and capacitances present between the layers. A layout versus schematic check (LVS) is performed, step
114
, where the extracted net-list is compared to the design implementation created in step
104
. LVS ensures that the design layout is a correct realization of the intended circuit topology. Any errors such as unintended connections between transistors, or missing connections/devices, etc. must be corrected in the design layout before proceeding to post-layout simulation, step
116
. The post-layout simulation is performed using the extracted net-list which provides a clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that can occur due to signal delay mismatches. Once post-layout simulation is complete and all errors found by DRC are corrected, the design is ready for fabrication and is sent to a fabrication facility.
As electronic circuit densities increase and technology advances, for example, in deep sub-micron circuits, skilled designers attempt to maximize the utilization of the design layout and manufacturability and reliability of the circuit. For example, the density can be increased, redundant vias added, and the like. Creation of a design layout and performing DRC become critical time consuming processes. Performing a DRC and manipulation of the design layout often requires manual interaction from the designer. A reliable, automated technique for improving the design layout is needed.
SUMMARY
Accordingly, it has been discovered that automated techniques to correct certain rule violations with respect to non-design geometries can be used, simplifying and automating the design layout of an electronic circuit, whether embodied as a design encoding or as a fabricated electronic circuit.
Accordingly, in one embodiment, correcting minimum spacing rule violations between wide class objects of non-design geometries is accomplished by deducting an enlarged wide class object of a first non-design geometry from a second non-design geometry; wherein the enlarged wide class object of the first non-design geometry is formed by enlarging a wide class object of the first non-design geometry at one or more non-virtual edges of the wide class object of the first non-design geometry but not at one or more virtual edges of the wide class object of the first non-design geometry wherein the wide class object of the first non-design geometry has at least one virtual edge.
In another embodiment, deducting an enlarged wide class object of the second non-design geometry from the first non-design geometry is performed; wherein the enlarged wide class object of the second non-design geometry is formed by enlarging a wide class object of the second non-design geometry at one or more non-virtual edges of the wide class object of the second non-design geometry.
In another embodiment, the wide class object of the first geometry is of a same wide class as the wide class object of the second design geometry and more area is deducted from the first non-design geometry and the second non-design geometry than is needed to meet a minimum spacing rule.
In another embodiment, the wide class object of the first geometry is of a different wide class as the wide class object of the second design geometry and only enough area is deducted from the first non-design geometry and the second non-design geometry to meet a minimum spacing rule.
In another embodiment, enlarging the wide class object of the first non-design geometry is accomplished by creating corner clearance areas from non-virtual convex vertices of the wide class object of the first non-design geometry; creating edge to edge spacing clearance areas from non-virtual edges of the wide class object of the first non-design geometry; and combining the corner clearance areas and the edge to edge spacing clearance areas to form the enlarged wide class object of the first non-design geometry.
In another embodiment, creating corner clearance areas is accomplished by stretching non-virtual edges that form the non-virtual convex vertices of the wide class object of the first non-design geometry by a minimum spacing rule amount creating stretched edges; and sizing the stretched edges by the minimum spacing rule amount.
In another embodiment, creating edge to edge spacing clearance areas is accomplished by sizing non-virtual edges of the wide class object of the first non-design geometry by a minimum spacing rule amount.
In another embodiment, the first non-design geometry and the second non-design geometry are dummy geometries.
The foregoing is a summary and thus
Levin Naum B
Siek Vuthe
Sun Microsystems Inc.
Zagorin O'Brien & Graham LLP
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