Memory testing for built-in self-repair system

Details Memory testing for built-in self-repair system Memory testing for built-in self-repair system

2000-09-20

2004-04-27

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S718000, C365S200000, C365S201000

Reexamination Certificate

active

06728910

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to test and repair of semiconductor memory.
2. Description of Related Art
Semiconductor memory is a crucial resource in modern computers, being used for data storage and program execution. With the exception of the central processor itself, no other component within the computer experiences as high a level of activity. Traditional trends in memory technology are toward greater density (more memory locations, or “cells”, per part), higher speed and improved reliability. To some extent, these goals are inconsistent. For example, as memory density increases, the incidence of defects also rises. As a result, production yields of high-density memory devices with zero defects would be so low as to render them prohibitively costly. However, an alternative to building perfect devices is to include spare memory cells along with the primary memory of the device. Additional internal circuitry detects faulty cells, and swaps good cells for known-bad ones. Therefore, as long as there are sufficiently many working cells to replace the defective ones, a fully functional memory device can be made. The primary memory is sometimes referred to as “accessible memory”, and the spare memory as “redundant memory”. The techniques for internally detecting faulty memory cells and for replacing them with working cells are commonly referred to as “built-in self-test” (hereinafter, “BIST”) and “built-in self-repair” (hereinafter, “BISR”), respectively. BIST and BISR are instrumental in obtaining acceptable yields in the manufacture of high-performance semiconductor memory.
Conventional memory devices are typically organized as a matrix of rows and columns, in which each individual cell has a unique row/column address. A popular memory architecture incorporating the above-described BIST and BISR techniques configures spare memory locations as redundant rows. Thus, a nominal m×n memory device is actually configured as m rows and n columns of accessible memory, with p rows (and n columns) of redundant memory. Redundant memory rows are not part of the nominal m×n address space of the device, except when used to replace defective accessible memory rows. Circuitry within the memory device itself performs both the test (BIST) and repair functions. During BIST, this circuitry generates test patterns to identify faulty memory locations. Then, during BISR, it reroutes internal connections, circumventing these locations and effectively replacing defective rows of accessible memory with working redundant rows.
Most currently used BIST/BISR methods test not only the accessible memory, but the redundant rows that are swapped in to replace accessible memory locations that have failed. The memory is certified as repairable only if there are enough functional redundant rows to replace every faulty row in the accessible memory; otherwise, it is considered non-repairable. A memory test generally involves writing a specific bit pattern to a range of memory cells, then reading back the values actually stored and comparing them to the desired pattern. In practice, this task is not easily accomplished. There are a variety of failure mechanisms that the BIST algorithm must be able to recognize. The simplest of these, in which memory cells are “stuck” in a particular logic state, are readily detected. Others, such as interaction between adjacent rows or columns of the memory, are less obvious. A memory cell that is susceptible to adjacent row adjacent column interaction, for example, tends to follow the logic transitions of neighboring cells; this condition would not be apparent, however, if the cell were tested alone. In order to reveal interaction-related failures, memory tests are often conducted using alternating bit patterns in adjacent rows or columns of the memory matrix (commonly referred to as a “checkerboard” pattern).
It is often desirable to incorporate improvements in the BIST to achieve better fault coverage. However, in conventional BIST/BISR methods, the test and repair functions are highly interdependent. Consequently, modification of the BIST algorithm may entail corresponding changes to the BISR mechanism. Therefore, even minor changes to the test algorithm may necessitate difficult or extensive modification of the repair circuitry. In some cases, the modified BIST may be inconsistent with the existing BISR circuitry.
A typical BIST/BISR method employs two BIST stages (also referred to herein as BIST “runs”). In the first stage, the accessible memory is tested row-by-row until a defect is encountered. The row containing the defect is then replaced by the first available redundant row and retested. This process continues until all of the accessible memory has been tested, or until there are no more redundant rows to use as replacements. In the first case, a second BIST run is performed, verifying all of the accessible memory. In the second case, the device is flagged as non-repairable. The two-stage method suffers from several drawbacks, among them the fact that it may overlook adjacent row interaction defects in the memory. Since the method tests accessible memory and redundant memory separately, it cannot detect interaction between adjacent accessible and redundant rows. A further disadvantage of the conventional two-stage method is that the total test time is not predictable. The duration of the test is dependent on the number of bad accessible memory rows, each of which has to be replaced and retested. Since there is no way to know the test time in advance, precise test scheduling during production is impossible.
More complex, multi-stage BIST/BISR methods can be devised to provide better fault detection. However, such methods suffer from the drawback that the array size in each of the BIST runs is different. This demands a separate BIST engine for each run, each specifically configured for its respective array size. The additional circuitry complicates the problem of upgrading BISR circuitry to support BIST enhancements.
The data retention test is another critical evaluation of the memory that may be performed by the BIST. This involves writing a test pattern to the memory, waiting for some prescribed interval, and then reading the memory to determine whether the test pattern was retained. The need for separate BIST tests for each array size in the conventional BIST/BISR method can significantly prolong data retention tests. The test interval is typically on the order of a second, so the retention test may account for the majority of the test time in a BIST run. Consequently, a memory device incorporating a three-stage BIST could require roughly three times as long to test as one with a one-stage BIST.
In view of the above-mentioned problems, it would be desirable to have a method for self-test and self-repair of semiconductor memory devices in which the BISR mechanism is substantially independent of the BIST mechanism, such that changes to the BIST could be accommodated with little or no modification to the BISR. Under the method, the BISR should be consistent with upgrading fault coverage capability in the BIST, e.g., readily supporting improved versions of tests for adjacent row interaction, data retention, etc. In addition, a system embodying the method should be efficient and permit estimation of total test time.
SUMMARY OF THE INVENTION
Conventional two-stage BIST/BISR methods may provide inadequate fault coverage, since they do not test for adjacent row interaction. While more complex BIST/BISR methods can be devised to provide better fault detection, such methods are often complicated by the fact that the array size in each of the BIST runs is different. For example, a memory device can be tested in three stages: the first stage tests the redundant memory along with the adjacent accessible row, the second stage tests the accessible memory along with the adjacent redundant row, and the third stage verifies the repaired accessible memory. However, this method requires a

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