Method and circuit for accelerating redundant address matching

Details Method and circuit for accelerating redundant address matching Method and circuit for accelerating redundant address matching

2003-01-06

2004-03-16

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189070, C327S057000

Reexamination Certificate

active

06707734

ABSTRACT:

The present invention relates generally to semiconductor devices having redundant elements for replacing defective elements and specifically to a circuit and method for accelerating accesses to and from such devices.
BACKGROUND OF THE INVENTION
The use of redundant memory elements in dynamic random access memory (DRAM) is widespread because it allows acceptable manufacturing yields of large memory devices even with aggressive semiconductor process design rules. Common industry practice includes extra rows and columns within memory arrays. The extra rows and columns are selectively substituted for memory elements within the array that are found to be defective during testing of the memory array. Therefore, many memory devices that otherwise would have rendered flawed by one or more point defects can be repaired and made fully operative.
The replacement of defective memory elements with redundant memory elements is controlled by address decoding logic which detects specific defective addresses or defective address ranges and redirects memory accesses to redundant memory elements. Typically, this capability is implemented by adding comparator circuits for detecting an equality between a portion of the memory access address and specific values (referred to as a redundant row address) permanently set in a repaired device. These specific values are permanently set in the repaired device at test time by laser programmable fuses and the like. When the address comparator detects an access to a defective memory element, special logic suppresses the regular access mechanism and a redundant element is accessed instead.
Referring to
FIG. 1
, the traditional approach to implementing row redundancy in a synchronous interface DRAM device is shown generally by numeral
100
. The address input to a memory is captured in a register
102
. The row selection (or X) portion of the address output from the register
102
is sent to a number of redundant row address comparators, C
1
and C
2
(only two are shown for simplicity), as well as to an X-address predecoder block
103
. Each of the redundant row address comparators C
1
and C
2
has redundant row addresses R
1
and R
2
as its second input value. If the input row address is equivalent to one of the redundant row addresses, the comparator for that particular redundant address activates its associated output line, OL
1
or OL
2
. The output lines OL
1
and OL
2
are logically combined with redundancy enable signals E
1
and E
2
respectively via AND gates
105
. The results of the logical combinations are match signals, M
1
and M
2
, which indicate when the current row address matches a redundant row address. A corresponding redundant address is thereby enabled. The match signals M
1
and M
2
are NOR-ed together via NOR gate
107
for generating an enable signal for regular word line drivers
106
.
A global word line driver control signal WLC controls the timing for asserting both the regular and redundant word line drivers
106
and
108
respectively. The global word line driver control signal cannot be asserted until all the inputs to both the regular and redundant word line drivers,
106
and
108
, have settled. The delay avoids glitching in any word lines and possibly corrupting data within the memory array. The earliest time at which it is possible to assert the global word line control signal WLC is defined by the sum of the clock-to-out delay of the address register
102
and the propagation delays of the address comparator C
1
and the memory access signal combining NOR gate
107
.
Therefore, as illustrated in the example above, the problem with conventional redundancy based repair of semiconductor memory is that it can limit the ability to achieve low access latency and a high rate of access operation. The delay is caused by the addition of a relatively long logic delay between the time the memory receives an address and the time the specified set of memory cells are accessed. A memory access cannot proceed until the address has been checked by all applicable enabled redundancy comparators and determined not to be the address of a defective element, thus increasing the delay. It is an object of the present invention to obviate and mitigate the above mentioned disadvantages.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a latched comparison circuit for generating complementary latched output signals. The latched comparison circuit comprises a comparator circuit for comparing an input address with a redundant address for generating a comparison output signal. The latched comparison circuit further comprises a flip-flop circuit coupled to the comparison output signal for latching the comparison output signal and for providing complementary latched comparison output signals in response to a clock signal.
In accordance with a further aspect of the invention there is provided a method for generating complementary latched output signals comprising the following steps. An input address is compared with a redundant address for generating a comparison output signal. The comparison output signal is latched in response to a memory clock signal for providing complementary latched comparison output signals.
In accordance with yet a further aspect of the invention there is provided a circuit for reducing a time delay between selecting a normal address and a redundant address in a memory device having normal and redundant memory elements. The circuit comprises a comparison circuit for comparing an input memory address with a redundant memory address for generating a comparison output signal. The circuit further comprises a flip-flop coupled with the comparison circuit for latching the comparison output signal in response to a memory clock signal. The comparison circuit compares the addresses before the memory clock signal is asserted.


REFERENCES:
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patent: 5640365 (1997-06-01), Imamiya et al.
patent: 5841712 (1998-11-01), Wendell et al.
patent: 6400617 (2002-06-01), Aikawa et al.
patent: 0 881 571 (1998-12-01), None
patent: 0 929 036 (1999-07-01), None

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