Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-10
2004-09-28
Thomas, Tom (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S317000
Reexamination Certificate
active
06798012
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor non-volatile memory devices, and more particularly to a dual-bit source-side injection cell which has two floating gates for storing two bits of information.,
DESCRIPTION OF THE RELATED ART
There are two types of hot-electron injection flash EEPROM cells, classified by the location of the charge injection in the programming mode. They are commonly referred to as “drain-side” and “source-side” injection cells. In a drain-side injection cell, electrons are injected onto the floating gate from a region in the source-drain channel near the drain junction; while in a source-side injection cell, electrons are injected onto the floating gate from a region in the source-drain channel near the source junction.
Source-side injection cell has superior programming characteristics because it requires substantially lower programming current than the drain-side injection cell. Therefore, source-side injection cells are more suitable for low power and low voltage applications.
FIGS. 1A and 1B
are cross-section views of two types of source-side injection cells.
FIG. 1A
shows a triple-polysilicon source-side injection cell
100
disclosed in the U.S. Pat. No. 5,280,446 by Ma et al., incorporated herein by reference.
FIG. 1B
shows a double-polysilicon cell
150
disclosed in U.S. Pat. No. 5,029,130 by Yeh, incorporated herein by reference. A common feature of the cell structures
100
and
150
is that the channel between the source and drain junctions is covered partly by a floating gate and partly by a select-gate. Such structures are commonly referred to as a split-gate structure.
A structural difference between cells
100
and
150
is that the triple-polysilicon cell
100
has five operating terminals (select-gate
101
, control-gate
102
, drain
104
, source
105
, and substrate
106
), while the double-polysilicon cell
150
has four operating terminals (select-gate
151
, drain
154
, source
155
, and substrate
156
). Note that drain junction
154
is deeper than source junction
155
to increase floating gate
153
to drain
154
overlap capacitance for improved voltage coupling from the drain to the floating gate. Cell
100
has a channel portion
109
.
While the programming mechanisms of cell structures
100
and
150
are similar (e.g., source-side injection, shown by the arrows P in FIGS.
1
A and
1
B), their erase operations differ. In the triple-polysilicon cell
100
, during erase, the electrons are tunneled from floating gate
103
to drain
104
via a thin gate-dielectric
107
. This is shown by the arrow E in FIG.
1
A. However, in the double-polysilicon cell
150
, the electrons are tunneled from floating gate
153
to select-gate
151
via a thin inter-polysilicon dielectric
158
at a pointed corner of the floating gate
153
. This is shown by the arrow E in FIG.
1
B.
The manufacturing process for the double-polysilicon cell
150
is less costly and has a shorter fabrication cycle time than the triple-polysilicon cell
100
, because cell
150
requires one less polysilicon by layer and thus fewer masking steps. However, the definition of sharp process development associated with the and the delicate inter-polysilicon dielectric
153
of cell
150
is quite tedious.
An important factor that directly impacts the cell-size and the array-size is the choice of array architecture. In conventional arrays, one bit-line contact is normally required for every two cells. In such “direct contact” arrays, the bit-line contact occupies a substantial portion of the cell area. In an alternative “virtual ground” (or so-called “contactless”) array approach, the number of contacts per cell is greatly reduced (typically by a factor of about 10×), hence resulting in smaller cell-size and smaller array-size. However, because of its inherently high bit-line resistance, the virtual-ground array suffers from slower memory access speed.
Memory cells
100
and
150
are single-bit cells (i.e., there is one floating gate in each cell for storing one bit of information).
FIG. 2
is a cross-sectional view of a dual-bit triple-polysilicon cell structure
200
disclosed in U.S. Pat. No. 5,278,439 by Ma et al., incorporated herein by reference. Cell structure
200
is a six-terminal cell (select-gate
201
, control-gates
202
A and
202
B, “drain/source” junctions
204
and
205
, and substrate
206
) with two floating gates
203
A and
203
B. Each floating gate
203
A,
203
B stores one bit of information. Structurally, cell
200
is obtained by merging two adjacent mirror-facing single-bit cells of the kind in
FIG. 1A
so that the source junctions (i.e., source junction
105
in
FIG. 1A
) and a select-gate portion (corresponding to channel portion
109
in
FIG. 1A
) of the merged cells are eliminated. This results in a smaller cell-size per bit. Junctions
204
and
205
are interchangeable in their functions (as a source or a drain) depending on whether the right bit (e.g., information stored in floating gate
203
A) or the left bit (e.g., information stored in floating gate
203
B) is accessed. Control-gates
202
A and
202
B are reciprocally identical.
A drawback of cell
200
is that it has a longer effective channel-length than the single-bit cell
100
. This results in higher channel resistance and thus a lower read-current in the cell. The lower read-current generally results in slower memory access time. Thus, the small cell-size and lower read-current of cell
200
makes this cell suitable for high density memory applications which generally have less stringent memory access time requirements.
With memory density and the access speed as the criteria, flash memory applications are generally divided into two commodity categories: (1) for code storage applications in which data access speed has greater importance than memory density, and (2) for mass-storage (or data storage) applications in which memory density has much greater importance than the access speed. Despite the small size of the dual-bit cell
200
, its costly triple-polysilicon manufacturing process and complicated six-terminal operations, make it an unattractive option for the cost sensitive high density applications.
The NAND-type flash memory cell approach has become popular for mass-storage applications because of its small cell-size and its relatively simple double-polysilicon process. However, because its operation requires high voltage in both positive and negative polarities, designing the array decoders to fit within the tight cell-pitch limits future advancement of this technology. Also, because of its small read-current, the NAND-type array is more susceptible to noise immunity and suffers from slow sensing speed, and thus presents a greater challenge in achieving the target operation margins as technology scaling continues.
Thus, a new dual-bit cell with a comparable per bit cell-size to that of the NAND-type array but with higher read-current and fewer operating terminals, and which requires a simple process is needed for such applications as mass-storage.
SUMMARY OF THE INVENTION
In accordance with the present invention, a double-polysilicon cell structure is capable of storing two bits of information. In one embodiment, the cell structure includes a first junction and a second junction separated by a channel region, the first and second junctions being in a body region. A first and a second floating gates extend over the channel region. A select-gate has a portion located between the two floating gates, and the select-gate extends over at least a portion of each of the two floating gates.
In another embodiment, the first floating gate extends over a first portion of the channel region and over a portion of the first junction, and the second floating gate extends over a second portion of the channel region and over a portion of the second junction.
In another embodiment, each of the first and second floating gates has at least one slanted surface forming a sharp edge.
In another embodiment, an inter-polysilicon dielectric layer insulating
Ma Yueh Yale
Pang Chan-Sui
Lee Eugene
Townsend and Townsend / and Crew LLP
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