Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-31
2004-01-27
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06684382
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to the field of semiconductor devices. More particularly, the invention relates to a method and apparatus for correcting for microloading effects.
2. Description of the Related Art
One common step in modern approaches to integrated circuit (IC) production is the use of an etching process after exposure of photoresist on the semiconductor to electromagnetic radiation (e.g. light).
There are number of different etching technologies and methods available including, plasma etching and several types of ion beam etching. In some instances over etching, e.g. etching for an extended period of time compared to the normal etching period, has been used to reduce feature sizes. However, over etching worsens the microloading effect.
Of particular importance during etching processes is maintaining uniformity. Uniformity refers to evenness of etching for critical dimension, as well as uniformity of etching across a wafer and from wafer to wafer. At the microscopic level, etching rates and profiles depend on features size and feature separation. Microscopic uniformity problems can be grouped into several categories including pattern-dependent etch effects, generally referred to as a microloading. More specifically, microloading refers to the dependence of the etch rate on feature separation for identically sized features and it results from the depletion of reactants when the wafer has a local, higher-density area.
From a terminology standpoint, critical dimension simply refers to the dimension (e.g. width) of a feature in the relevant direction. For example, a feature corresponding to a transistor can be conceived of as a one dimensional object on the mask since the length will change, but the critical dimension will not. Thus, for example if the transistors are being prepared with a target critical dimension of 1 &mgr;m, there can be multiple transistors with different lengths, e.g. some 5 &mgr;m, some shorter, some longer, but all might be designed to have critical dimension of 1 &mgr;m. (Note, a single mask may include similar features having different critical dimensions.)
Current optical proximity correction techniques are not well suited to accounting for microloading effects. Further, if existing approaches are used in a straightforward fashion they may be computationally infeasible with present day computer systems and hardware.
Accordingly, what is needed is a method and apparatus for correcting for microloading effects. Also suitable masks for producing integrated circuits that have been corrected for microloading effects. (As used herein, the term masks includes reticles.)
SUMMARY
A method and apparatus for providing correction for microloading effects is described. Hybrid proximity correction techniques are used to make the problem computationally more feasible. Specifically, if model based optical proximity correction techniques were used alone, the problem would be extremely complicated and further changes made to correct for optical errors would interact with changes made to correct microloading errors.
The approach groups feature edges in a layout into those edges, edges or edge segments, with a large edge separation (group B), e.g. greater than n, and those having less than that separation (group A). More specifically, the straight line distance from neighboring edges to a given edge can be determined and edges, or edge segments, that are further than the given amount n placed into group B. The value of n is process technology dependent, for an example &lgr;=248 nm wavelength process, n=1.5 &mgr;m. Edges having a separation equal to n are placed into either group A or group B, in one embodiment they are placed in group B to be corrected for microloading effects.
The group B features are then corrected for microloading effects, or etch effects, using rules based correction. Rules based corrections can be applied extremely rapidly since there is minimal computational complexity as the layout is scanned for features, edges, and/or edge segments matching the rule criteria and then the rules are applied. For example, a rule might adjust an edge with a separation of 2.0 &mgr;m by 30 nm.
Next, both groups of edges, e.g. the entire layout portion being corrected, can be corrected using model based optical proximity correction (MOPC). The MOPC is applied using the output of the rule based correction as the ideal, or reference layout. Conceptually this can be viewed as the MOPC is trying to bring the layout so that after optical effects occur the pattern will be such that it is shaped as was computed is better (based on the rules) to account for the later occurring etch process.
In some embodiments, the ordering of the etch and optical effects are switched; however, such embodiments are likely to give less accurate corrections, but may still be useful. Approaches for developing appropriate etch and optical models are described as well. The models can be generated using measurements taken from test exposures. This ensures that the generated models are calibrated for the particular lithography process being used including the stepper, the resist, the etch, etc. In some embodiments, uncalibrated models are used based on assumed data or theoretical computations. This may be appropriate for testing purposes, if suitable test exposures cannot be obtained, and/or if only slight changes to the lithography process for a previously calibrated model are being made, etc.
REFERENCES:
patent: 4037918 (1977-07-01), Kato
patent: 4231811 (1980-11-01), Somekh et al.
patent: 4426584 (1984-01-01), Bohlen et al.
patent: 4456371 (1984-06-01), Lin
patent: 4812962 (1989-03-01), Witt
patent: 4895780 (1990-01-01), Nissan-Cohen et al.
patent: 4902899 (1990-02-01), Lin et al.
patent: 5051598 (1991-09-01), Ashton et al.
patent: 5182718 (1993-01-01), Harafuji et al.
patent: 5208124 (1993-05-01), Sporon-Fiedler et al.
patent: 5241185 (1993-08-01), Meiri et al.
patent: 5242770 (1993-09-01), Chen et al.
patent: 5256505 (1993-10-01), Chen et al.
patent: 5302477 (1994-04-01), Dao et al.
patent: 5308741 (1994-05-01), Kemp
patent: 5316878 (1994-05-01), Saito et al.
patent: 5324600 (1994-06-01), Jinbo et al.
patent: 5328807 (1994-07-01), Tanaka et al.
patent: 5334542 (1994-08-01), Saito et al.
patent: 5340700 (1994-08-01), Chen et al.
patent: 5352550 (1994-10-01), Okamoto
patent: 5364716 (1994-11-01), Nakagawa et al.
patent: 5424154 (1995-06-01), Borodovsky
patent: 5447810 (1995-09-01), Chen et al.
patent: 5480746 (1996-01-01), Jinbo et al.
patent: 5496666 (1996-03-01), Chu et al.
patent: 5498579 (1996-03-01), Borodovsky et al.
patent: 5503951 (1996-04-01), Flanders et al.
patent: 5523186 (1996-06-01), Lin et al.
patent: 5527645 (1996-06-01), Pati et al.
patent: 5532090 (1996-07-01), Borodovsky
patent: 5537648 (1996-07-01), Liebmann et al.
patent: 5538815 (1996-07-01), Oi et al.
patent: 5539568 (1996-07-01), Lin et al.
patent: 5553273 (1996-09-01), Liebmann
patent: 5553274 (1996-09-01), Liebmann
patent: 5565286 (1996-10-01), Lin
patent: 5573890 (1996-11-01), Spence
patent: 5595843 (1997-01-01), Dao
patent: 5620816 (1997-04-01), Dao
patent: 5631110 (1997-05-01), Shioiri et al.
patent: 5635316 (1997-06-01), Dao
patent: 5636002 (1997-06-01), Garofalo
patent: 5636131 (1997-06-01), Liebmann et al.
patent: 5657235 (1997-08-01), Liebmann et al.
patent: 5663017 (1997-09-01), Schinella et al.
patent: 5663893 (1997-09-01), Wampler et al.
patent: 5682323 (1997-10-01), Pasch et al.
patent: 5702848 (1997-12-01), Spence
patent: 5705301 (1998-01-01), Garza et al.
patent: 5707765 (1998-01-01), Chen
patent: 5723233 (1998-03-01), Garza et al.
patent: 5725969 (1998-03-01), Lee
patent: 5740068 (1998-04-01), Liebmann et al.
patent: 5761075 (1998-06-01), Oi et al.
patent: 5766804 (1998-06-01), Spence
patent: 5766806 (1998-06-01), Spence
patent: 5807649 (1998-09-01), Liebmann et al.
patent: 5815685 (1998-09-01), Kamon
patent: 5821014 (1998-10-01), Chen et al.
patent: 5825647 (1998-10-01), Tsudaka
patent: 5827623 (1998-10-01), Ishida et al.
patent: 5847959 (1998-12-01),
Bever Hoffman & Harms LLP
Harms Jeanette S.
Niebling John F.
Numerical Technologies Inc.
Whitmore Stacy
LandOfFree
Microloading effect correction does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microloading effect correction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microloading effect correction will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3239849