Process for fast cell placement in integrated circuit design

Details Process for fast cell placement in integrated circuit design Process for fast cell placement in integrated circuit design

2001-06-12

2004-03-09

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06704915

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to cell placement, and particularly to the placement of cells within approximated coordinates during a redesign or modification of an integrated circuit (IC).
It is common in IC design to base new designs on ICs already developed for a prior use. One problem in redesigning ICs is that some cells of the prior design must be placed in close proximity in the new design. This is particularly important where two cells cooperate to perform certain tasks. If one cell is moved quite far from the other, wire lengths may affect metal layer routing, parasitic capacitance and signal timing.
Present automated processes for redesigning integrated circuits often move cells quite far from the original location, resulting in adverse effects resulting from increased wire length. Moreover, automated processes are not capable of performing re-design where the number of rows or columns of cells in a given direction is altered from one design to another. For example, a re-design that adds to the number of y-oriented columns of elements increases the number or length in the x-direction. Thus, expansion or contraction of a design along rows (x-direction) requires a corresponding addition or subtraction to the number of columns (y-direction) of cells. Automated processes are not helpful to perform changes in columns. Accordingly, there is a need for an automated process, operating under the control of a computer, that performs transformation of existing IC designs to new designs by approximated coordinates of the cells to correct the placement of the cells in correspondence with existing design rules.
SUMMARY OF THE INVENTION
In accordance with the present invention, the distribution of cells in a first integrated circuit chip layout is altered to position the cells in a second integrated circuit chip layout. An x,y grid is established for the first and second integrated chip layouts such that each cell has identifying x,y coordinates in the first layout and a height in the y-direction. A number of columns is established in the second layout based on the bounds of the second layout in the x-direction. The cells are sorted to the columns in the order of cell x-coordinates to establish new x-coordinates for each cell based on the x-coordinates of the respective column. Each column has a height in the y-direction. The cells are then sorted in each column to establish y-coordinates for each cell based on the height of the cells in the column and the height of the column.
In some embodiments of the process, the cells are sorted to the columns by calculating a minimum column height H
min
, for all columns. A recursive algorithm is applied to distribute the cells of each column to x-positions between adjacent columns.
According to another aspect of the process, the recursive algorithm identifies a plurality of positions between adjacent columns, and identifies maximum and minimum non-overlapping ranges of x-coordinates for each position.
According to another aspect of the invention, the cells are sorted in each column to establish y-coordinates by computing a distance real_D[i] between identifying y-coordinates of adjacent cells of each column based on the first layout. A distance min_D[i] is computed in the y-direction between the adjacent cells based on the heights of the adjacent cells. An overlap over_D[i] is computed based on a difference between real_D[i] and min_D[i].
According to another aspect of the invention, a correction factor corr_D[i] is added to the y-coordinate of each cell.
According to another aspect of the invention, a computer useable medium contains a computer readable program comprising code that causes the computer to alter the distribution of cells from the first layout to the second layout.


REFERENCES:
patent: 5495419 (1996-02-01), Rostoker et al.
patent: 5625568 (1997-04-01), Edwards et al.
patent: 6058254 (2000-05-01), Scepanovic et al.
patent: 6074430 (2000-06-01), Tsukiboshi
patent: 6370673 (2002-04-01), Hill

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