Integrated circuit chip with high-aspect ratio vias

Details Integrated circuit chip with high-aspect ratio vias Integrated circuit chip with high-aspect ratio vias

2000-05-25

2004-03-23

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S774000

Reexamination Certificate

active

06710447

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to integrated circuit chips and more specifically to an integrated circuit chip with high-aspect ratio vias where the vias are filled using a channel collimator effect
BACKGROUND ART
While manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the “damascene” technique starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithogaphically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and a barrier layer is deposited to coat the walls of the first channel opening to ensure good adhesion and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as “barrier layer” herein). A seed layer is then deposited on the barrier layer to form a conductive material base, or “seed”, for subsequent deposition of conductive material. A conductive material is then deposited in the first channel openings and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metalization process, which is called the “dual damascene” technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin stop nitride over the fist channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride.
A via step photoresist is used in a photolithographic process to designate via areas over the first channels. A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas.
After the via is formed, an adhesion/barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the adhesion/barrier layer. This is followed by a deposition of the conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. Thus, a thin adhesion layer formed of an adhesion material, such as titanium, is first deposited on the dielectric in the channels and vias to ensure good adhesion and good electrical contact of the subsequently deposited adhesion/barrier layers to underlying doped regions and/or conductive channels. This is followed by the barrier layer to prevent diffusion, materials such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN) are used as barrier materials for copper. Adhesion/barrier layer stacks formed of adhesion/barrier materials such as tantalum/tantalum nitride (Ta/TaN), titanium/titanium nitride (Ti/TiN), and tungsten/tungsten nitride (W/WN) have been found to be useful as adhesion/barrier material combination for copper interconnects. In some cases, no adhesion layer is placed between the barrier and oxide. For example, only TaN monolayer is used sometimes because the TaN has good adhesion to the oxide.
After deposition of the adhesion/barrier material, a seed layer is deposited by ionized metal plasma (IMP) deposition. Generally, the metal deposited is copper or a copper alloy. The copper seed layer provides an electrode for the subsequent copper electroplating which will fill the channels and vias.
The common problems associated with most of the seed layer deposition techniques are poor sidewall step coverage and conformality, i.e., the seed layer thickness is much higher in wide-open areas, such as on top of the channel oxide layer, in the upper portion of the sidewalls of the channels and vias, and bottom of the channels than in the lower portion of the sidewalls of the channels and vias. To guarantee a minimum seed layer thickness anywhere in the channel or vias, including at the lower portion of the sidewalls, the seed layer thickness in wide-open areas tends to be much higher. As the width of the channels and vias have decreased in size due to the size reduction in the semiconductor devices, an excessively thick seed layer in the wide-open areas interferes with the subsequent filling of the channel and vias with conductive materials leading to the formation of voids. These voids lead to connection and electro-migration failures.
A solution, which would form uniform seed layers in vias and result in an improvement in the subsequent filling of the vias by conductive materials, has long been sought, but has eluded those skilled in the art. As the semiconductor industry moves from aluminum to copper and other types of high conductivity materials, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides an integrated circuit with high-aspect ratio vias in which the upper channel is used as a collimator for the vias during the ionized metal plasma deposition of the seed layer. This results in a seed layer with reduced overhang in the vias enhancing the subsequent filling of the vias by a conductive layer and preventing the formation of voids in the vias.
The present invention further provides an integrated circuit with high-aspect ratio vias in which the upper channel after lining with an adhesion/barrier layer is used as a collimator for the vias during the ionized metal plasma deposition of the seed layer over the adhesion/barrier layer. This results in a seed layer with reduced overhang in the vias enhancing the subsequent filling of the vias by a conductive layer and preventing the formation of voids in the vias.
The present invention further provides an integrated circuit with high-aspect ratio vias in which the upper channel is used as a collimator with a via entrant angle of greater than about 69 degrees during th

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