Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-02-14
2004-03-30
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S014000
Reexamination Certificate
active
06715136
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for the simulation of an electrical circuit, which can be described by a layout.
The behavior of integrated electrical circuits is often influenced by parasitic effects that are caused by lines.
Undesired capacitive effects are of particular importance in this context that are caused by electrical conductors which run in direct proximity or are arranged next to one another. Electrical conductors can be described by capacitances and by nonreactive resistances. Such capacitive effects caused by conductors are therefore also referred to as parasitic capacitances.
Parasitic capacitances cannot be disregarded in various analyses of integrated electrical circuits, for example when determining the delay or crosstalk. Electrical circuits of great complexity can become unusable due to undesired effects caused by such parasitic capacitances. On account of the large dimension of the network list—generated by an extraction—with parasitic elements, taking account of parasitic capacitances in the simulation of electrical circuits leads to performance problems both in the extraction and in the subsequent analysis steps.
The extraction is often performed in a planar manner. Although the resulting network list comprises all the relevant information, the performance of the extraction and of the subsequent analysis steps on the basis of such a network list proves to be unsatisfactory on account of the very large volumes of data to be handled.
One alternative to this is a hierarchical procedure, in which all the instances of a given cell are entered identically into the network list. It is thereby disadvantageous that the different environments of cell entities are not taken into account and, as a result, an accurate simulation of the electrical circuit is not possible.
A further possibility consists in outputting each entity of a cell as a dedicated variant. With this procedure, it is disadvantageous that the resulting network list contains a very large number of cells and is correspondingly unwieldy in its further processing. Performance problems arise here as well.
A solution approach according to which cells are classified in accordance with their environment is not known in the prior art.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method of simulating an electrical circuit that can be described by its layout, and to provide corresponding computer is software as well as nd data carriers, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enables an advantageous simulation of electrical circuits, and takes into account effects caused by parasitic capacitances.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of simulating an electrical circuit that can be described by a layout with a multiplicity of cells. The layout has the following features:
the cells have one or more networks described by geometrical data and subdivided into one or more models of electrical circuit elements;
the cells have information about those layers on which the networks are present; and
the cells have references to further cells.
The method comprises the following steps:
a) extracting node information from a layout;
b) determining and recording coupling capacitance values of the networks with isolated consideration of the cells;
c) determining and recording environment-dependent coupling capacitance values of the networks for all of the cell entities;
d) determining and recording intrinsic capacitance values of the networks for each cell;
e) determining and recording intrinsic capacitance values of the networks for all of the cell entities;
f) calculating a respective comparison capacitance value for each network with isolated consideration of the cells;
g) calculating differential capacitance values of each network with respect to a respective comparison capacitance value for all of the cell entities;
h) classifying the cell entities of each cell into different variants for all of the networks by using the differential capacitance values as a basis; and
i) simulating a behavior of the electrical circuit using the variants of the cell entities determined in the preceding step.
In accordance with an added feature of the invention, the above step h) is replaced with the following:
h1) defining a tolerance value T and a value for an index k;
h2) selecting a cell from the layout;
h3) selecting a network of the cell selected in step h2);
h4) selecting a k-th cell entity of the cell;
h5) determining the differential capacitance value D
k
for the k-th cell entity from a difference in a sum of the intrinsic and lateral capacitance values for the network selected in step h3) and from a sum of the intrinsic and lateral capacitance values of the network in the k-th cell entity;
h6) testing whether a variant V exists for which |D
k
−D
v
|≦T and, if the variant V exists, continuing with step h8), otherwise continuing with step h7);
h7) forming a new variant V with D
v
=D
k
;
h8) classifying the k-th cell entity of the cell into the variant V;
h9) incrementing the index k;
h10) testing whether a k-th cell entity of the cell exists and, if a k-th entity exists, continuing with step h4), otherwise:
h11) testing whether a further network exists in the cell under consideration, if the further network exists, selecting the network, defining a value for the index k, and continuing with step h4).
In this case, the intention is to utilize the hierarchy existing in the layout and to take account of the different environments of various entities of identical cells in the resulting network list.
According to the invention, an electrical circuit can be described by a layout and, after the extraction, by a network list.
The layout contains a geometrical description of all the circuit elements arranged on the electrical circuit. This geometrical description is designed in particular in the form of polygons or rectangles.
In accordance with another feature of the invention, steps h2) to h11) are repeated for further cells of the network list.
In accordance with an additional feature of the invention, the above steps h6), h7), and h8) are replaced with the following, starting with a second network under consideration,
h6′) testing whether a variant V exists for which |D
k
−D
v
|≦T and, if the variant does not exist, continuing with step h7′);
h6″) testing whether the k-th cell entity and the cell entities already contained in the variant V have previously been classified in different variants V and, if not, continuing with step h8′);
h7′) forming a new variant V with D
v
=D
k
; and
h8′) classifying the k-th cell entity of the cell into the variant V.
In accordance with a further feature of the invention, coupling capacitances and intrinsic capacitances are extracted in one step as opposed to extracting separately.
In a preferred embodiment of the invention, there are extracted only coupling capacitances or only intrinsic capacitances.
In this case, the layout is subdivided into a multiplicity of cells which each have one or more networks, which are described by geometrical data and contain one or more models of electrical circuit elements. By way of example, a simple cell may contain all those polygons which together represent an inverter. Furthermore, the cells contain information about those layers of the electrical circuit on which the networks or the circuit elements are present. In this case, each polygon is assigned that layer on which the corresponding network or the corresponding electrical circuit element is modeled on the electrical circuit. Furthermore, many cells have references to further cells. In this case, it is possible to insert or instantiate cells into other cells. By way of example, one cell can be inserted as often as desired into other cells. The networks of instantiated cells
Garbowski Leigh M.
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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