Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-08-21
2004-04-20
Verbrugge, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S170000, C711S172000, C711S201000, C711S202000
Reexamination Certificate
active
06725322
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a technique of high-speed writing on a memory card, and particularly to a technique which is applied effectively to the allotment of logical address to a flash memory.
BACKGROUND ART
For external memory devices of portable personal computers and multi-functional terminal units, memory cards have prevailed in a short time. In the presence of recent demands of enhanced performance of memory cards, the semiconductor memory included in a memory card is, for example, a flash memory which is electrically erasable and rewritable and can hold a huge amount of data without the need of a battery.
According to the study conducted by the inventors of the present invention, the flash memory used for the memory card has a data write operation in which before data is written to addresses, old data in the addresses is erased. This erasing operation takes place in a unit of sector (e.g., a sector has 512 bytes) or a unit of block (a block has 8 sectors, which have 4 k bytes).
The memory card transacts data with a host unit in a unit of cluster (e.g., a cluster has 4 k bytes or 2 k bytes), and the flash memory reads or writes a cluster of data at a time.
The memory card is rendered the logical address allotment of the flash memory before it is shipped. Specifically, a data area for storing data to be transacted with the host unit is set next to an area for various control information including the master boot record, file allocation table and directories.
The IC card of this kind is described in detail in, for example, publication “Electronic Materials”, pp. 22-26, edited by Masashi Ooshima, published by a company of Koogyo Choosa Kai on Dec. 1, 1990, and this publication describes the technical trend of various IC cards.
In regard to the above-mentioned data erasing technique for the memory card, the inventors of the present invention have found the following problems.
Since the logical address allotment is in accord with the order of physical address of the flash memory, logical addresses of clusters and those set to the flash memory are out of accord with each other, which compels the abovementioned pre-writing data erasure to take place in a unit of sector or in units of sector and block in combination, resulting in an increased number of times of erasing operation and a longer data write time.
The host unit has serial operations of data transfer, erasure and writing by expending time for each operation, which retards the speed-up of data writing to the flash memory.
It is an object of the present invention to provide a method of logical address allotment and a method of data writing on a memory card which are capable of speeding up the data writing based on the matching of blocks and clusters, the efficient erasure of block data, and the efficient data writing.
These and other objects and novel features of the present invention will become apparent from the following description of the specification taken in conjunction with the accompanying drawings.
DISCLOSURE OF THE INVENTION
The present invention is designed to use an offset storage section which stores an offset value and an offset calculation section which implements a computation for the offset value in the offset storing section and input logical addresses, and sets the logical addresses which are render the offset based on the calculation by the offset calculation section to physical addresses of the nonvolatile memory so that a unit of block and a unit of cluster match with each other.
The present invention is designed to have the abovementioned offset storage section included in an area of the nonvolatile memory.
The present invention is designed to store the offset value in the ID area of the nonvolatile memory.
The present invention is designed to form sector blocks each including physical addresses of a certain number of sectors of a nonvolatile memory, set the starting physical address of an arbitrary sector block among the sector blocks to the starting logical address of a data area, and set the data area of logical address down to the last sector of physical address.
The present invention is designed to form sector blocks each including physical addresses of a certain number of sectors of a nonvolatile memory, set the starting physical address of an arbitrary sector block among the sector blocks to the starting logical address of the data area, set the data area of logical address down to the last sector of physical address, and set the remaining data area to physical addresses by starting at the starting physical address.
The present invention is designed to form, for each of two nonvolatile memories, sector blocks each including physical addresses of a certain number of sectors, set the starting logical address of a data area to the starting physical address of an arbitrary sector block of one nonvolatile memory, set the remaining logical addresses to sector blocks of the two nonvolatile memories alternately on a block by block basis down to the last sectors of physical address of the two nonvolatile memories, and set the remaining data area to physical addresses of the one nonvolatile memory by starting at the starting physical address.
The present invention is designed to form, for each of nonvolatile memories of 2N in number, sector blocks each including physical addresses of a certain number of sectors, set the starting logical address of a data area to the starting physical address of an arbitrary sector block of one nonvolatile memory among the 2N nonvolatile memories, set the remaining logical addresses sequentially to sector blocks of the 2N nonvolatile memories on a block by block basis down to the last sectors of physical addresses of the 2N nonvolatile memories, and set the remaining data area to the one nonvolatile memory by starting at the starting physical address.
The present invention is designed to make the physical address of the sector block, to which the logical address is set, nearest to the starting address of the data area.
The present invention is designed to store data to be written, which is transferred from a host unit, on a memory card temporarily, read out control information from a block of a nonvolatile memory, erase the block, and store data to be written next, which is transferred from the host unit, on the memory card temporarily, while storing the data, which has been stored temporarily on the memory card, in the block-erased sectors of the nonvolatile memory.
The present invention is designed to include a first step of reading out control information from a sector block of a nonvolatile memory which firstly undergoes data writing and implementing the block erasure of the sector block, a second step of reading out control information from an arbitrary sector of the nonvolatile memory which secondly undergoes data writing, while storing data to be written, which has been stored temporarily on a memory card, into sectors of nonvolatile memory, and storing temporarily data to be written next on the memory card, and a third step, which takes place after control information is all read out of the sector block of the second-writing nonvolatile memory, of storing the data which has been stored temporarily on the memory card into sectors of the first-writing nonvolatile memory, while erasing the read-out sector block, and reading out control information from an arbitrary sector of the second-writing nonvolatile memory, with the second and third steps being repeated down to the nonvolatile memory of the 2N-th data writing.
Based on these schemes, for multiple nonvolatile memories, erasure, writing and data transfer from a host unit to the memory card can take place concurrently, whereby the data write time can be reduced significantly.
Consequently, the performance of memory card can be enhanced significantly.
REFERENCES:
patent: 5598370 (1997-01-01), Niijima et al.
patent: 5630093 (1997-05-01), Holzhammer et al.
patent: 5799168 (1998-08-01), Ban
patent: 6459644 (2002-10-01), Mizushima et al.
patent: 0 557 736 (1993-09-01), None
patent: 5-27924
Inoue Manabu
Matsumura Kenzo
Onuki Yuichiro
Shiota Shigemasa
Shiraishi Atsushi
Miles & Stockbridge P.C.
Namazi Mehdi
Renesas Technology Corp.
Verbrugge Kevin
LandOfFree
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