Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-10-20
2004-03-16
Myers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S107000, C710S110000, C710S308000, C710S306000, C710S315000
Reexamination Certificate
active
06708246
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to techniques for coding motion images and the like and particularly to devices coding data more efficiently.
2. Description of the Background Art
In recent years multimedia technology has been increasingly studied in various fields and particularly important are techniques for coding image signals having enormous amounts of data. In transmitting and storing such image data, it is essential to use a data compression technique to reduce the amount of the data.
In general, image data has redundancy of a significant level attributed to a correlation between adjacent pixels, a human visual characteristic, and the like. A data compression technique used to suppress such a redundancy of image data and hence to reduce an amount of data to be transmitted is referred to as high-efficiency coding. In the high-efficiency coding, efficiently reducing data entails an adaptive processing.
The adaptive processing requires another, software-controllable processor, which can be related to a technique “Development of media-processor incorporated 1-chip MPEG2 422@ML Video, Audio, System Encoder,” Technical Report of IEICE, ED99-60, SMD99-34, ICD99-42. This document describes that a coding, large scale integrated circuit (LSI) including an incorporated processor depending on the process(es) as required and an external, central processing unit (CPU) are used and that the Coding LSI and the external CPU require an interface therebetween.
If an integrated processor and an external CPU share a bus, the ownership of the bus is transferred therebetween. For example, when the bus slave (the integrated processor) issues a bus request (BUSR) to the bus master (the external processor) and the bus master can release the bus, the bus master issues a bus acknowledgement (BUSA) and the ownership of the bus is thus transferred. As such, if the bus ownership is frequently transferred between the integrated processor and the external CPU, the coding LSI's processing efficiency will be disadvantageously reduced.
Furthermore, conventionally an interrupt factor for the integrated processor and that for the external CPU are allotted to a single status register, resulting in a cumbersome interrupt processing in the coding device.
SUMMARY OF THE INVENTION
The present invention contemplates a signal processing device capable of processing data with a reduced cycle and thus more efficiently.
The present invention also contemplates a signal processing device capable of reducing an interrupt processing load to process data more efficiently.
In one aspect of the present invention, the signal processing device includes an integrated processor, and an interface controlling a bus ownership between the integrated processor and an external processor, wherein the interface includes a first detect portion detecting an access of the integrated processor to an external device, a second detect portion detecting a write to a predetermined register, and a bus control portion asserting a bus request to the external processor in response to a result of detection provided by the first detect portion, and negating a bus request to the external processor in response to a result of detection provided by the second detect portion.
With the bus control portion thus configured, if the signal processing device accesses the external device successively, the ownership of the bus is only transferred once. As such, the device can process data more efficiently.
In another aspect of the present invention, the signal processing device includes an integrated processor, and an interface controlling a bus ownership between the integrated processor and an external processor, wherein the interface includes a first status register allotted an interrupt factor for the integrated processor and a second status register distinguished from the first status register and allotted an interrupt factor for the external processor.
Since the first and second status registers may be provided separately, the integrated processor is not interrupted due to an interrupt factor for the external processor. Thus the signal processing device can process data more efficiently.
Preferably, the signal processing device further includes a video processing unit connected to the integrated processor via an internal bus to code a video signal.
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“A Single-Chip MPEG2 422@ML Video, Audio and System Encoder with a 162-MHz Media-Processor and Dual Motion Estimation Cores” by Kawamoto et al., Technical Report of IEICE, ED99-60, SMD99-34, ICD99-42 (Jun. 1999), pp. 39-44.
Ishihara Kazuya
Segawa Hiroshi
McDermott & Will & Emery
Myers Paul R.
Phan Raymond N
Renesas Technology Corp.
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