Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-09-03
2004-04-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S151000, C438S622000, C438S637000, C438S633000, C438S634000, C438S643000, C438S645000, C438S672000, C438S677000, C438S691000, C438S692000, C438S700000, C438S745000, C438S760000, C438S906000, C438S963000
Reexamination Certificate
active
06723626
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. More particularly, the present invention relates to a wet processing method of protecting a copper wiring pattern.
2. Description of the Related Art
With the enlargement of a chip size and the miniaturization of a minimum processing dimension, a parasitic capacitance and a wiring line resistance increase to cause a wiring delay. In order to avoid it, an interlayer insulating film with a low dielectric constant is used for decrease of the parasitic capacitance. Also, a copper wiring with a small resistance is used for decrease of the wiring line resistance. Thus, by using the interlayer insulating film with the low dielectric constant for decrease of the capacitance C and using copper for the wiring line for decrease the resistance R, the wiring delay (&Xgr;RC) can be reduced.
In order to decrease the wiring line resistance, it is also important to decrease an average wiring line length. Since the average wiring line length is inversely proportional to the number of wiring layers, a multiple-layer technique of the wiring layers is important. For this purpose, a damascene wiring structure technique and a chemical mechanical polishing (CMP) technique become essential which can attain the multiple-layer structure without involving concave and convex portions on the surface of a lower layer.
The CMP polishing is a step for precisely polishing a surface by using abrasive material in a process for manufacturing a semiconductor device. The CMP polishing precisely flattens an upper portion of a lower layer so as not to form any concave and convex portions on an upper layer. The manufacturing step is the very fine step. Thus, the high technique is required for the abrasive material, a polishing condition, a polishing apparatus, a rinsing method and the like.
The problems in the CMP of the conventional technique will be described below. The conventional technique will be described below with reference to FIG.
1
.
FIG. 1
is a diagram showing a step of rinsing after a CMP process is ended.
FIG. 1
shows a wafer
101
, pure water
102
, a pure water nozzle
104
, a rinse solution
103
and a rinse solution nozzle
105
. Here,
FIG. 1
shows a step of rinsing the back side of the wafer
101
, in which the rinsing of the front side of the wafer
101
is ended after an unnecessary portion of a wiring film is CMP-polished.
On the wafer
101
are formed semiconductor devices such as semiconductor element, interlayer insulating films, damascene wiring lines and the like.
The pure water
102
is of a super high purity used to manufacture a semiconductor. The pure water
102
has a function of covering the front surface of the wafer
101
and thereby protecting impurities and the rinse solution
103
from going from back side to the front side.
The pure water nozzle
104
is provided to discharge the pure water
102
onto the front surface of the wafer
101
.
The rinse solution
103
is used to remove abrasive residuals and contaminants which go onto the back side through the CMP polishing operation on the front side of the wafer
101
.
The rinse solution nozzle
105
is provided to discharge the rinse solution
103
onto the back side of the wafer
101
.
The front surface of the wafer
101
is rinsed after the formation of the copper damascene wiring line by the CMP polishing operation. After that, as shown in
FIG. 1
, the back side of the wafer
101
is rinsed by the rinse solution
103
. At this time, the pure water
102
is discharged onto the front surface of the wafer
101
so that the contaminants on the back side do not go onto the side of the front surface.
The states of the damascene wiring line at this time will be described with reference to
FIGS. 2A and 2B
.
FIGS. 2A and 2B
are cross sectional views showing the damascene wiring lines of the wafer
101
.
FIGS. 2A and 2B
show a substrate
111
, an insulating film
112
, a barrier film
113
, a wiring film
114
and a wiring line groove
115
.
The substrate
111
is a semiconductor substrate on which semiconductor elements, (interlayer) insulating films, damascene wiring lines and the like are formed. The substrate
111
may be a semiconductor substrate formed of silicon, or a semiconductor substrate on which an insulating film formed of silicon dioxide and silicon nitride is formed.
The insulating film
112
is formed using an organic material such as a polymer of a hydrocarbon system or using an inorganic material such as silicon dioxide.
The barrier film
113
is a thin metal film. The barrier film
113
protects the interlayer insulating film
112
from being exposed to plasma, and also protects the wiring line film
114
from being diffused into the insulating film
112
. The barrier film
113
is formed of titanium nitride, tantalum and the like.
The wiring line film
114
is formed of a metal with a low specific resistance. The wiring line film
114
is formed in a wiring line groove in the insulating film, and functions as the damascene wiring line. For example, the wiring line film
114
is formed of copper.
In
FIG. 2A
, the side of the front surface of the substrate
111
is rinsed after the damascene wiring line is formed in the wiring line groove
115
through the CMP polishing operation. After that, the back side of the substrate
111
is rinsed by the rinse solution
103
as shown in FIG.
1
. When the back side is rinsed, the pure water
102
is sent onto the front side. The pure water
102
is sent in order to protect the rinse solution
103
for rinsing the back side from going onto the front surface. Next,
FIG. 2B
shows a cross sectional view when the back side rinsing is ended. In
FIG. 2B
, it is known that side slits are formed on the boundary between the wiring line film
114
and the barrier film
113
.
In this way, the side slits occurs irrespectively of the stage at which the rinsing of the surface is ended after the completion of the CMP polishing operation. This is because the wiring line film
114
of copper is etched with the CMP polishing solution slightly remaining on the front surface and the pure water
102
. Also, although being not shown, there may be a possibility that a pit is induced on the front surface through the etching.
Consequently, not only a sectional area of the wiring line is reduced, but also a location dependency occurs. That is, concave and convex portions are formed, which may result in a disturbance in a step coverage of an interlayer insulating film.
FIG. 3
is a view showing a different process of a rinsing after the CMP process is ended.
FIG. 3
shows a wafer
101
, pure water
102
, a pure water nozzle
104
, a rinse solution
103
, a rinse solution nozzle
105
, an end portion rinse solution
106
and an end portion nozzle
107
. Here,
FIG. 3
shows the process in which after an unnecessary portion of a wiring line film is polished through the CMP polishing operation, the rinsing on the front surface of the wafer
101
is ended, and the rinsing of the back side thereof and the removal of metal components of a surface edge are carried out at the same time.
The end portion rinse solution
106
is used for rinsing and removing the metal portion on the edge of the surface.
The end portion nozzle
107
is provided to supply the end portion rinse solution
106
.
The other structures from the wafer
101
to the rinse solution nozzle
105
are as mentioned above. Thus, their description is omitted.
Also, in this case, the phenomenon shown in
FIGS. 2A and 2B
is brought about similarly to the above-mentioned case. The side slit is induced on the boundary of the barrier film of the damascene wiring line. Thus, it is difficult to effectively decrease the wiring line resistance. There may be a problem even in the step coverage of the interlayer insulating film.
In conjunction with to the above-mentioned description, Japanese Laid Open Patent Application (JP-A, 2001-89747) discloses a polishing composition and a polis
Kubo Akira
Tsuchiya Yasuaki
Isaac Stanetta
McGinn & Gibb PLLC
NEC Electronics Corporation
Niebling John F.
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