System and method for trap address mapping for fault isolation

Details System and method for trap address mapping for fault isolation System and method for trap address mapping for fault isolation

1997-12-12

1999-08-17

Palys, Joseph E.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395591, 711202, G06F 1100

Patent

active

059405872

ABSTRACT:
The invention relates to the alteration of a segment and an offset used to form an effective address of the default interrupt handler routine. The method comprising a number of steps. First, a trap address of a default interrupt handler routine is provided. This trap address includes a segment and an offset normally used to calculate the effective address via conventional circuitry. However, an unique segment is produced by performing an arithmetic operation on the segment. Thereafter, another arithmetic operation is performed to produce a unique segment. These unique segment and offset values may still be used by the conventional circuitry to still produce the same effective addresses so that only one default interrupt handler routine is required. While this alteration produces a unique segment and offset which can be assigned to an interrupt, the segment and offset are modified appropriately to still use a common default interrupt handler.

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