Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-10-02
2004-03-23
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S640000, C438S739000, C438S792000
Reexamination Certificate
active
06709965
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a novel bond pad structure employed to accommodate a subsequent wire bond design, and the method of forming the novel bond pad structure.
2. Description of Prior Art
Wire bonds have been used to connect a specific semiconductor chip to an external component such as a module or package. A wire bond, comprised of gold wire is first bonded to a specific region of the semiconductor chip with the other end of the wire then connecting to the external component. The conductive region of the semiconductor chip used to accommodate the gold wire bond is a conductive bond pad structure which communicates with the active device regions of a semiconductor substrate via multiple levels of metal interconnect structures. A critical aspect of the wire bond procedure is the integrity of the conductive bond pad structure to which the wire will be connected to. Bond pad structures comprised of conductive materials such as aluminum based layers, have to survive several processes prior to the wire bond procedure. For example the semiconductor wafer comprised with numerous semiconductor chips has to be thinned to approximately to a thickness of about 15 mils via a backside grounding procedure, prior to dicing or separation of the individual semiconductor chips. This procedure can damage a bond pad structure, specifically if a raised topography of the bond pad structure is exposed during the wafer thinning procedure. In addition an unprotected bond pad structure can be damaged in terms of scratches and defects during transporting of the pre-diced semiconductor wafer to an another area of a semiconductor facility in which dicing and wire bonding functions will be performed. Damaged bond pad structure can adversely influence the quality of a gold wire bond in terms of increased resistance at the wire bond—bond pad structure interface, which in turn deleteriously influence the reliability and yield of a package comprised with individually wire bonded semiconductor chips.
This invention will describe a novel bond pad structure design, and a process sequence used for fabrication of the novel bond pad structure, in which the top surface of the bond pad structure is maintained below the top surface of the dielectric layer in which the bond pad opening was defined in. This novel topographical situation offers protection to the bond pad structure during subsequent pre-dicing procedures such as wafer thinning and transportation. Prior art such as Wu et al, in U.S. Pat. No. 6,287,950, Paranthaman et al, in U.S. Pat. No. 6,261,704 B1, Peng et al, in U.S. Pat. No. 5,731,243, and Shih et al, in U.S. Pat. No. 6,361,704 B1, and Chen, in U.S. Pat. No. 6,303,459 B1, describe bonding pad structures and methods of forming these bond pad structures. None of the prior art however describe the present invention in which a bonding pad opening is isotropically and anisotropically defined to enable the top surface of a subsequently formed bond pad structure to be located entirely in the bond pad opening, featuring a top surface below the top surface of the dielectric layers in which the bond pad opening was defined in.
SUMMARY OF THE INVENTION
It is an object of this invention to form a bond pad structure on an exposed portion of an underlying metal interconnect structure of a semiconductor substrate to accommodate a subsequent wire bond, which in turn is used to physically connect a semiconductor chip to an external package.
It is another object of this invention to define a bond pad opening in a composite insulator stack with the top insulator layer of the composite insulator stack defined isotropically and laterally pulled back from the underlying insulator layers of the composite insulator stack, which are opened anisotropically.
It is still another object of this invention to form the bond pad structure entirely in the bond pad opening in the composite insulator stack, with the top surface of the bond pad structure located below the top surface of the composite insulator stack.
In accordance with the present invention a bond pad structure design, and the method of forming the bond pad structure, featuring a bond pad opening formed isotropically and anisotropically in a composite insulator stack, and featuring formation of the bond pad structure located entirely in the bond pad opening, is described. After formation of an upper level metal interconnect structure a composite insulator stack comprised of an underlying silicon oxide layer, a silicon nitride layer, and an overlying, thick silicon oxide layer, is deposited. Definition of a bond pad opening in the composite insulator stack is next accomplished via a selective isotropic etch of the thick silicon oxide layer, laterally undercutting the overlying defining photoresist shape. Anisotropic dry etching of the silicon nitride layer and of the underlying silicon oxide layer result in a bond pad opening exposing a portion of the top surface of the upper level metal interconnect structure, with the bond pad opening featuring an isotropic opening in the thick silicon oxide component, laterally pulled back from the underlying silicon nitride layer. Deposition of a metal layer, thinner than the thick silicon oxide layer, is followed by patterning of the metal layer resulting in the definition of a bond pad structure located entirely in the bond pad opening, with the top surface of the bond pad structure lower than the top surface of the composite insulator stack.
REFERENCES:
patent: 4827326 (1989-05-01), Altman et al.
patent: 5552343 (1996-09-01), Hsu
patent: 5731243 (1998-03-01), Peng et al.
patent: 6261704 (2001-07-01), Paranthaman et al.
patent: 6287950 (2001-09-01), Wu et al.
patent: 6303459 (2001-10-01), Chen
patent: 6361704 (2002-03-01), Shih et al.
Stanley Wolf Ph.D. and Richard N. Tauber Ph.D. in Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, 1986, pp. 191-195, 531-534, 539-542, 581.
Chen Kuo-Chou
Hsu Huai-Jen
Ackerman Stephen B.
Brewster William M.
Coleman W. David
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Aluminum-copper bond pad design and method of fabrication does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Aluminum-copper bond pad design and method of fabrication, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Aluminum-copper bond pad design and method of fabrication will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3235579