Semiconductor element and semiconductor memory device using...

Details Semiconductor element and semiconductor memory device using... Semiconductor element and semiconductor memory device using...

2001-07-27

2004-01-06

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S066000, C257S386000

Reexamination Certificate

active

06674117

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element suited for integration with a high density and a semiconductor memory device implemented by using the same.
Heretofore, polycrystalline silicon transistors have been used as elements for constituting a static random access memory device (referred to as SRAM in abbreviation). One of the relevant prior art techniques is described in T. Yamanaka et al: IEEE International Electron Device Meeting, pp. 477-480 (1990). By making the most of polycrystalline silicon transistors, integration density of the integrated circuit can be enhanced, the reason for which can be explained by the fact that the polycrystalline silicon transistor can be formed in stack or lamination atop a conventional bulk MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) formed on a surface of a semiconductor substrate with an insulation film being interposed between the polycrystalline silicon transistor and the bulk MOSFET. In the SRAM, implementation of a memory cell for one bit requires four bulk MOSFETs and two polycrystalline silicon transistors. However, because the polycrystalline silicon transistors can be stacked atop the bulk MOSFETs, a single memory cell of the SRAM can be implemented with an area which substantially corresponds to that required for the bulk MOSFETs.
As another preceding technique related to the invention, there may be mentioned a single-electron memory described in K. Nakazato et al: Electronics Letters, Vol. 29, No. 4, pp. 384-385 (1993). It is reported that a memory could have been realized by controlling electron on a one-by-one basis. It is however noted that the operation temperature is as very low as on the order of 30 mK.
As a further prior art technique related to the invention, there may be mentioned one which is directed to the study of RTN (Random Telegraph Noise) of MOSFET, as is disclosed in F. Fang et al: 1990 Symposium on VLSI Technology, pp. 37-38 (1990). More specifically, when a drain current of a MOSFET is measured for a predetermined time under the constant-voltage condition, there makes appearance such phenomenon that state transition takes place at random between a high-current state and a low-current state. This phenomenon is referred to as the RTN, a cause for which can be explained by the capture or entrapping of a single electron in a level node existing at an interface between silicon (Si) and silicon oxide (SiO
2
) and the release therefrom, whereby the drain current undergoes variations. However, the RTN remains only as a subject for a fundamental study concerning the current noise in the MOSFET, and any attempt or approach for positively making use of the RTN in practical applications has not been reported yet at all.
At present, the technology for processing a semiconductor integrated circuit with high fineness has developed up to such a level where any attempt for realization of higher fineness will encounter difficulty. Even if it is possible technologically, there will then arise a problem that intolerably high cost is involved due to the necessity for much sophisticated technique. Under the circumstances, a great demand exists for a fundamentally novel method of enhancing the integration density in the fabrication of semiconductor integrated circuits instead of relying on a method of implementing the semiconductor elements constituting the semiconductor integrated circuit simply by increasing the fineness thereof.
On the other hand, the polycrystalline silicon transistor known heretofore is basically equivalent to a variable resistor element in the respect that resistance between a source and a drain of the polycrystalline silicon transistor can be controlled by a gate voltage. Consequently, implementation of a memory cell of a SRAM requires as many as six semiconductor elements inclusive of the conventional MOSFETs formed in a silicon substrate.
By contrast, in the case of a DRAM (Dynamic Random Access Memory), information or data of one bit can be stored in a memory cell constituted by one MOSFET and one capacitor. For this reason, the DRAM enjoys reputation as a RAM device susceptible to implementation with the highest integration density. However, because the DRAM is based on such a scheme that electric charge is read out onto a data wire of which capacitance is non-negligible, the memory cell thereof is required to have capacitance on the order of several ten fF (femto-Farads), which thus provides a great obstacle to an attempt for further increasing fineness in implementation of the memory cells.
By the way, it is also known that a nonvolatile memory device such as a flash EEPROM (Electrically Erasable and Programmable Read-Only Memory) can be realized by employing MOSFETs each having a floating gate and a control gate. Further, as a semiconductor element for such a nonvolatile memory device, there is known MNOS (Metal Nitride Oxide Semiconductor) element. The MNOS is designed to store charge at interface between a SiO
2
-film and a Si
3
N
4
-film instead of the floating gate of the flash EEPROM. Although the use of the MOSFET equipped with the floating gate or the MNOS element is certainly advantageous in that one-bit data can be held or stored by one transistor over an extended time span, a lot of time is required for the rewriting operation because a current to this end has to flow through the insulation film, whereby the number of times the rewriting operation can be performed is limited to about 100 millions, which in turn gives rise to a problem that limitation is imposed to the applications which the nonvolatile memory device can find.
On the other hand, the one-electron memory device discussed in the Nakazato et al's article mentioned hereinbefore can operate only at a temperature of cryogenic level, presenting thus a problem which is very difficult to cope with in practice. Besides, a cell of the single-electron memory is comprised of one capacitor and two active elements, which means that a number of the elements as required exceeds that of the conventional DRAM, to a further disadvantage.
As will be appreciated from the forgoing, there exists a great demand for a semiconductor element which requires no capacitance elements, differing from that for the DRAM and which can exhibit stored function by itself in order to implement a memory of higher integration density than the conventional one without resorting to the technique for implementing the memory with higher fineness.
SUMMARY OF THE INVENTION
In the light of the state of the art described above, it is an object of the present invention to provide an epoch-making semiconductor element which allows a semiconductor memory device to be implemented with a lesser number of semiconductor elements and a smaller area and which per se has data or information storing capability while requiring no cooling at a low temperature such as cryogenic level.
Another object of the present invention is to provide a semiconductor memory device which can be implemented by using the semiconductor elements mentioned above.
A further object of the invention is to provide a data processing apparatus which includes as a storage the semiconductor memory device mentioned above.
For achieving the above and other objects which will become apparent as description proceeds, it is taught according to a basic technical concept underlying the invention that capacitance between a gate and a channel of a semiconductor field-effect transistor element is set so small that capture of a single carrier (electron or hole) by a trap level can definitely and discriminately detected as a change in the current of the semiconductor field-effect transistor element. More specifically, correspondences are established between changes in a threshold value of the semiconductor field-effect transistor element as brought about by capture of a carrier in the trap and releasing therefrom and digital values of logic “1” and “0”, to thereby impart to the semiconductor field-effect transistor element a function or capability for storing data or

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