Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-11
2004-07-20
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S059000, C257S072000, C257S403000
Reexamination Certificate
active
06765265
ABSTRACT:
The present invention relates to a thin film transistor (hereafter TFT). In particular it relates to a manufacturing technology for improving the transistor characteristics of the TFT.
The various apparatuses which use TFTs include an active matrix substrate of a liquid crystal display which is formed on a transparent substrate such as a glass plate, and the near central region is designated to be the screen display region
81
as shown in
FIG. 12
(A). In this screen display region
81
, pixels are formed in blocks by data line
90
and scanning line
91
which are made of metal film, silicide film and conductive semiconductor film of aluminum, tantalum, molybdenum, titanium and tungsten. In each pixel, liquid crystal units
94
(liquid crystal cell) to which image signals are input through TFT
30
for pixel switching are formed. For data line
90
, a data side driving circuit
60
with a shift register
84
, a label shifter
85
, a video line
87
, and an analog switch
86
are formed. For the scanning line
91
, a scanning side driving circuit
79
with a shift register
88
and the label shifter
89
are formed. In each pixel, a storage capacitor
40
is formed between the scanning line
91
and the capacity line
92
extending parallel to the scanning line
91
, which storage capacitor
40
possesses a function to raise maintenance characteristics of the electric charge at the crystal unit
94
. Sometimes, the storage capacitor
40
may be formed between the aforementioned scanning line
91
and the pixel electrode.
A CMOS circuit is formed by an N-type TFT
10
and a P-type TFT
20
in the data-side and the scanning-side circuits
60
and
70
as described in
FIG. 12
(B). Such CMOS circuit forms an inverter circuit having more than one step in the driving circuits
60
and
70
.
Hence, three types of TFT consisting of an N-type TFT
10
for a driving circuit, a P-type TFT
20
for a driving circuit and an N-type TFT
30
for pixel switching on the surface side of the substrate in the active matrix substrate
200
. However, the basic structure is common to these TFTs
10
,
20
and
30
. Hence, to avoid redundancy of description, only the structure and the production method of the N-type TFT for a driving circuit will be described using
FIGS. 13
,
14
,
15
and
16
.
On the active matrix substrate
200
, a bottom layer protection film
51
made of silicon oxide film is formed on the surface side of the substrate
50
, and a polycrystal semiconductor film
100
is formed in island-like pattern on the surface of the bottom layer protection film
51
. A gate insulation film
12
is formed on the surface of the semiconductor film
100
and a gate electrode
14
is formed on the surface of the gate insulation film
12
. The channel region
15
is formed, through the gate insulation film
12
, in the area of the gate electrode
14
towering in the semiconductor film
100
. A highly concentrated source region
16
and a highly concentrated drain region
17
are formed on both sides of the channel region
15
being self-aligned with respect to the gate electrode
14
. A source electrode
41
and a drain electrode
42
are electrically connected respectively to the highly concentrated source region
16
and the highly concentrated drain region
17
through the contact holes of the inter-layer insulation film
52
.
In order to produce the TFT
10
with above structure, first, a substrate
50
made of glass, etc. which is cleansed by super sound wave cleansing is prepared in
FIG. 14
(A).
Next, as described in
FIG. 14
(B), a bottom layer protection film
51
is formed covering entire surface of the substrate
50
under temperature conditions of about 150° C. to 450° C. substrate temperature.
Next, as described in
FIG. 14
(C), a semiconductor film
100
is formed on the surface of the bottom layer protection film
51
, during which time, heat deformation of the glass substrate
50
is prevented by applying a low temperature process. The low temperature process is a process in which the maximum temperature of the process (the maximum temperature to which the entire substrate reaches simultaneously) is below about 600° C. (preferably below about 500° C.). On the other hand, a high temperature process is a process in which the maximum temperature of the process (the maximum temperature to which the entire substrate reaches simultaneously) is more than about 600° C. Film formation under high temperature or heat oxidation of silicon is a high temperature process of 700° C. to 1200° C.
However, during a low temperature process, formation of polycrystal semiconductor film directly on the substrate is impossible, hence, first non-crystal semiconductor film
100
is formed using a plasma CVD method or low pressure CVD method, and then the semiconductor film
100
is crystallized as described below. The SPC method (Solid Phase Crystallization) or RTF method (Rapid Thermal Annealing) may be considered as a method of crystallization to be used here. However, with the application of laser annealing (ELA: Excimer Laser Annealing/crystallization process) in which XeCl excimer laser beam is irradiated, as described in
FIG. 14
(D), a rise in the substrate temperature is prevented and polycrystal Si with large granule diameter is obtained.
In this crystallization process, a laser beam (excimer laser) from the laser beam source
320
is irradiated, through the optical system
325
, towards the substrate
50
being mounted on the stage
310
as described in
FIG. 15
, for example. During this process, the line beam L
0
with the irradiation region L being longer in X-direction (for example, the line beam with laser pulse repeat frequency of 200 Hz) is irradiated on the semiconductor film
100
, and the irradiation region L is shifted in Y-direction. Here, the beam length of the line beam L
0
is 400 mm with an output intensity being 300 mJ/cm
2
, for example. Moreover, in shifting the irradiation region L of the laser beam, the line beam is scanned in such a manner that the section equivalent to 90% of the peak value of the laser intensity in the width direction overlaps for each region. As a result, non-crystal semiconductor film
100
fuses once and is polycrystallized after a cooling solidification process. During this process, because the irradiation time of the laser beam on each region is very short and because the irradiation region is local compared to the entire substrate, simultaneous heating of the entire substrate
50
with high temperature does not occur. For this reason, heat deformation or cracks are prevented for the glass substrate being used as the substrate
50
, though the glass substrate is inferior to the quarzt substrate in heat resistance.
Next, island-like patterning is performed on the polycrystal semiconductor film
100
using a photo lithography technique, as described in FIG.
14
(E).
Then, a gate insulation film
12
made of silicon oxide film is formed with respect to the surface side of the semiconductor
100
, as described in FIG.
16
(A).
Next, a conductive film
140
containing aluminum, tantalum, molybdenum, titanium and tungsten is formed by a sputter method as described in FIG.
16
(B).
Then a gate electrode
14
is formed by patterning the conductive film
140
, as described in
FIG. 16
(D), after forming a resist mask
301
on the surface of the conductive film
140
as described in
FIG. 16
(C).
Next, phosphate ions with dosage of about 10
15
cm
−2
, for example, are knocked-in with respect to semiconductor film
100
using the gate electrode
14
as a mask. As a result, the highly concentrated source region
16
and drain region
17
with an impurity concentration of about 10
20
cm
−3
are formed on the semiconductor film
100
being self-aligned with respect to the gate electrode
14
. The section of the semiconductor film
100
where impurities are not introduced becomes the channel region
15
.
Next, annealing is performed for activation after the formation of the inter-layer insulation film
52
, as described in FIG.
13
. Then,
Migliorato Piero
Miyasaka Mitsutoshi
Yudasaka Ichio
Flynn Nathan J.
Oliff & Berridg,e PLC
Sefer Ahmed N.
Seiko Epson Corporation
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