Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-01-27
2004-03-02
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S306000
Reexamination Certificate
active
06700146
ABSTRACT:
This application claims priority to Japanese Patent Application Number JP2002-024065 filed Jan. 31, 2002, which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having ferroelectric capacitors, particularly to a semiconductor memory device able to be made highly integrated and to have a large capacity, and a method for producing the same.
2. Description of the Related Art
Recently many studies have been made for nonvolatile memory devices that make use of ferroelectric materials exhibiting the unique electrical characteristic called “spontaneous polarization” (ferroelectric memory devices or ferroelectric random access memories (FeRAMs), see U.S. Pat. No. 4,873,664) because of their high write speed, high read speed, low operation voltage, and other features. These have the possibility of replacing not only usual nonvolatile memories, but also static random access memories (SRAMs), direct random access memories (DRAMs), and most other types of memories.
In memory devices utilizing the spontaneous polarization characteristic of ferroelectric materials, wide use is made of a type of memory cell having a select transistor in addition to a ferroelectric capacitor, that is, a memory cell having a structure of one transistor and one capacitor (1 Transistor/1 Capacitor, or just abbreviated as “1T1C”). This type of FeRAM is obtained by just replacing a paraelectric capacitor material in a usual DRAM memory cell by a ferroelectric material.
Various materials have been developed for use as ferroelectic materials, such as lead-based oxides of an ABO
3
type Perovskite crystal structure like Pb(Zr,Ti)O
3
(PZT) or (Pb,La)(Zr,Ti)O
3
(PLZT), and bismuth-layered compounds like SrBi
2
Ta
2
O
9
(SBT). Particularly, SBT exhibits a superior fatigue property of not degrading even after repeated polarization switching and a superior polarization saturation property of a low electric field causing polarization saturation, and thus is useful for reducing the operation voltage.
To replace DRAMs and to be used widely, it is necessary for FeRAMs to have a degree of integration and a storage capacity comparable with those of DRAMs. However, it has been difficult to increase the degree of integration of FeRAMs having the aforesaid 1T1C type memory cell structure.
For a higher degree of integration, it is necessary to decrease the area of the memory cell. A memory cell is a region for storing 1 bit of data in a memory. Theoretically, the minimum value of the area of a memory area is that occupied by a predetermined number of word lines and bit lines intersecting each other in this region when arranged at shortest intervals. For an FeRAM of the 1T1C structure, usually there are 1 word line and 2 bit lines for 1 bit. When these word line and bit lines are arranged at shortest intervals, if the minimum design rule in semiconductor processing is F, the theoretical minimum cell area of the above FeRAM is 8F
2
, the same as a DRAM.
Actually, in each 1-bit storage area in a FeRAM, there are two transistors and two ferroelectric capacitors. Further, in addition to word lines and bit lines, plate lines have to be provided. Therefore, it is impossible to arrange the word lines and bit lines at shortest intervals and so the real cell area is larger than 8F
2
.
On the other hand, a flash memory, which is also a semiconductor nonvolatile memory, has a minimum cell area as small as 4F
2
because there is only one transistor in its memory cell.
In order to realize a higher degree of integration and a larger storage capacity for FeRAMs, memory cells each consisting of one element such as in a flash memory have been developed in recent years.
For example, in the FeRAMs disclosed by Japanese Unexamined Patent Publication (Kokai) No. 9-116107 (referred to as Reference 1 hereinafter) and in Japanese Unexamined Patent Publication (Kokai) No. 2000-349248 (referred to as Reference 2 hereinafter), a plurality of ferroelectric capacitors are connected to a common node electrode that is connected to a bit line through a select transistor, and each ferroelectric capacitor acts as a memory cell storing 1 bit of data. That is, a ferroelectric memory of a one-capacitor (
1
C) structure is realized, so theoretically it is possible to obtain a minimum cell area of 4F
2
, the same as a flash memory.
Further, as proposed in Japanese Patent Application No. 2000-156089 (referred to as Reference 3 hereinafter), further integration is possible for a ferroelectric memory having not less than two stacked layers of the aforesaid
1
C structure obtained by forming a plurality of ferroelectric capacitors on a common node electrode. For example, theoretically, the minimum cell area can be as small as 2F
2
to 4F
2
.
Since the actual cell area is determined by the minimum design rule F of semiconductor devices, so far, the reduction in the minimum design rule F along with progress in photolithography and other microprocessing technology has been the most important means of increasing the degree of integration of integrated circuits.
However, as the degree of integration becomes higher and the minimum design rule for designing elements becomes smaller, the area of the ferroelectric capacitor will also become smaller and the capacitance of and the amount of charge stored in the ferroelectric capacitor will become smaller. As a result, the signal picked up by a sense amplifier will not be large enough, causing malfunction of the memory. This has been a problem in DRAMs, which have the same structure as FeRAMs, and therefore will also be a problem for FeRAMs for which higher integration is sought.
Usually, the method used to solve this problem was to give the lower electrode of the capacitor a three-dimensional structure. In case of the already high integrated DRAMs, for example, in the DRAM memory cell disclosed in Japanese Unexamined Patent Publication (Kokai) No. 6-29482 (referred to as Reference 4 hereinafter), capacitors were stacked in a three-dimensional structure to make the surface area of the capacitors as large as possible.
Summarizing the problem to be solved by the invention, however, in case of a FeRAM including crystalline thin films composed of several kinds of elements, it is difficult to form a uniform thin film on a lower electrode having a three-dimensional structure, thus practical use has not been achieved yet.
So far, development has focused on methods applicable to FeRAMs for increasing the capacitance of a capacitor while satisfying the requirement of a higher degree of integration. The idea is the same as that for DRAMs, for example, increasing the effective area of a capacitor in a ferroelectric memory of a 1T1C structure by giving it a three-dimensional structure.
For example, in the ferroelectric memory cell of the 1T1C structure disclosed in Japanese Unexamined Patent Publication (Kokai) No. 7-86528 (referred to as Reference 5 hereinafter), giving the ferroelectric capacitor a multi-layer capacitor structure makes it possible to increase the capacitor area equivalently without increasing the area actually occupied by the capacitor and to secure a stable amount of charge contained in a signal.
Further, in the ferroelectric memory cell of the 1T1C structure disclosed in Japanese Unexamined Patent Publication (Kokai) No. 10-242410 (referred to as Reference 6 hereinafter), by providing a first capacitor and a second capacitor above and below a select transistor, it becomes possible to increase the overall area of the capacitor in a memory cell without increasing the area of the memory cell.
However, because the ferroelectric memory cells disclosed in Reference 5 and Reference 6 have 1T1C structures, the cell area itself is large, so it is difficult to achieve a high degree of integration. Further, in References 1, 2, and 3, which disclose memory cells of a smallest cell area, methods are not disclosed for increasing the effective area of a capacitor in a ferroelectric memory of a
1
C structure.
SUMMARY OF THE INVENTION
A
Depke Robert J.
Holland & Knight LLP
Nguyen Cuong
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