Process layout of buffer modules in integrated circuits

Details Process layout of buffer modules in integrated circuits Process layout of buffer modules in integrated circuits

2002-09-25

2004-07-06

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06760896

ABSTRACT:

FIELD OF THE INVENTION
This invention concerns integrated circuit layout, and particularly to layout of ICs containing bus modules having repeater buffers.
BACKGROUND OF THE INVENTION
An integrated circuit chip (herein referred to as an “IC” or “chip”) comprises cells and connections between cells supported by a substrate. A cell is a group of one or more circuit elements, such as transistors, capacitors and other basic circuit elements, grouped to perform a function. Each cell may have one or more pins, which in turn may be connected to one or more pins of other cells by wires. A net comprises circuitry coupling two or more pins. A typical IC includes a large number of cells and requires complex wire connections between the cells. A typical chip has thousands, tens of thousands and even hundreds of thousands of pins which are connected in various combinations.
Signal buses, composed of plural wires, are formed on the IC to carry multi-bit data and control signals between various circuits on the IC. The Routing wires of the bus are often long, requiring repeater buffers in the wires to preserve signal integrity. Metal layers, separated by layers of insulator material, are configured to define circuit routing wires for connecting various elements of the IC. Usually certain metal layers, such as even-numbered metal layers, are dedicated to horizontal routing wires, and other metal layers, such as odd-numbered metal layers, are dedicated to vertical routing wires. Metal posts or channels between horizontal and vertical routing wires provide connection between them so signals and power can propagate through the IC.
In general the IC layout is defined by rectangular modules having a fixed width and variable height, each containing input and output pins. Each pin is assigned to one of two opposite sides of the module, such as either a bottom or top side, at a given coordinate, such as a horizontal coordinate. One or more output pins are assigned to each input pin and needs to be connected to it. Each input pin, together with all the outputs assigned to it, defines a net.
One continuing problem of IC design is to implement, or route, the nets of a bus using a minimal possible module height. Repeater buffers in the bus ordinarily add to the module height. There is a need for a bus design approach that minimizes the height of the bus, including its repeater buffers.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the invention, a bus is laid out on a core of an integrated circuit with pin channels arranged along at least one edge of the core orthogonal to routing lines through the core. Net wires are routed through the core along respective routing lines. Buffer channels are defined in the core across a plurality of routing lines, and buffers are in the buffer channels so that an input and output to respective buffers are on different routing lines. The net wires are redistributed across the buffers to connect the respective buffer input and output to a net wire to be buffered.
The buffers have at least one free routing line that does not correspond to a net wire. The net wire to be buffered is identified, and the net wires are routed so that (i) the net wire to be buffered is re-routed to the input and output of the buffer, (ii) the net wires on routing lines containing the input and output of the buffer are re-routed to the routing line of the net wire to be buffered and the free routing line, and (iii) all other net wires are routed along their respective routing lines.
In preferred embodiments, the process is carried out in a computer operating under control of a computer program code.


REFERENCES:
patent: 6110221 (2000-08-01), Pai et al.
patent: 6502231 (2002-12-01), Pang et al.
Tai et al., “Performance Driven Bus Buffer Insertion”, Apr. 1996, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol. 15 No. 4, pp. 429-437.

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