Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-10-21

2004-05-25

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

Reexamination Certificate

active

06741492

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to an improvement a soft error resistance property of a CMOS (Complementary Metal Oxide Semiconductor) static RAM Random Access Memory), and more particularly relates to a semiconductor memory device capable of avoiding a problem with fatal multi-bit errors.
2. Description of the Background Art
FIG. 14
is an equivalent circuit diagram of a general SRAM memory cell and shows two-bit memory cells MC
0
and MC
1
arranged adjacent to each other in a row direction. In reference to
FIG. 14
, first, memory cell MC
0
, as a one-bit memory cell circuit, will be described. Memory cell MC
0
has two driver transistors N
1
A and N
2
A, two access transistors N
3
A and N
4
A, and two load transistors P
1
A and P
2
A. Two driver transistors N
1
A and N
2
A and two access transistors N
3
A and N
4
A are formed of nMOS transistors while two load transistors P
1
A and P
2
A are formed of pMOS transistors.
A first inverter is formed of nMOS transistor N
1
A and pMOS transistor P
1
A while a second inverter is formed of nMOS transistor N
2
A and pMOS transistor P
2
A. One output terminal of the first and second inverters are connected to another input terminals of the second and first inverters, respectively, thereby storage nodes ma and /ma are formed.
A source, a gate and a drain of nMOS transistor N
3
A are connected to one memory terminal ma, a word line WL and one bit line BLA, respectively. A source, a gate and a drain of nMOS transistor N
4
A are connected to the other memory terminal/ma, word line WL and the other bit line/BLA, respectively.
With the above described connection, the SRAM memory cell circuit is formed. Memory cell MC
1
also has approximately the same configuration as that of the above described memory cell MC
0
.
Then, respective gates of respective access transistors N
3
A, N
4
A, N
3
B and N
4
B of the plurality of memory cells MC
0
and MC
1
, which are aligned in the same row, are connected to common word line WL. Thereby, the memory cells aligned in the same row are simultaneously accessed when word line WL is risen.
A plan view layout configuration of such an SRAM memory cell is disclosed in, for example, Japanese Patent Laying-Open No. 9-270468.
FIG. 15
is a schematic plan view showing a layout configuration of the conventional SRAM memory cell shown in the above described publication using two-bit memory cells MC
0
and MC
1
arranged adjacent to each other in the row direction. In reference to
FIG. 15
, each of memory cells MC
0
and MC
1
is formed on surfaces of an n-type well
102
and of a p-type well
103
formed on a surface of a semiconductor substrate. According to description of memory cell MC
0
, two nMOS transistors N
1
A and N
2
A, which become a pair of driver transistors, and two nMOS transistors N
3
A and N
4
A, which become a pair of access transistors, are formed within p-type well
103
. Two pMOS transistors P
1
A and P
2
A, which become a pair of load transistors, are formed within n-type well
102
.
Driver transistors N
1
A and N
2
A have drains formed of n-type impurity regions
105
a
2
, sources formed of n-type impurity regions
105
a
3
and gates
107
c
and
107
b
extending onto the regions between these drains and sources, respectively. Access transistors N
3
A and N
4
A have drains formed of n-type impurity regions
105
a
1
, sources formed of n-type impurity regions
105
a
2
and gates
107
a
extending onto the regions between these drains and sources, respectively.
Source
105
a
2
of access transistor N
3
A and drain
105
a
2
of driver transistor N
1
A are formed of a common n-type impurity region. In addition, source
105
a
2
of access transistor N
4
A and drain
105
a
2
of driver transistor N
2
A are formed of a common n-type impurity region. Respective gates
105
a
of access transistors N
3
A and N
4
A are integrated with a single word line.
Load transistors P
1
A and P
2
A are formed of drains formed of p-type impurity regions
105
b
1
, sources formed of p-type impurity regions
105
b
2
and gates
107
c
and
107
b
extending onto the regions between these drains and sources, respectively. Gate
107
c
of load transistor P
1
A and gate
107
c
of driver transistor N
1
A are formed of the common conductive layer while gate
107
b
of load transistor P
2
A and gate
107
b
of driver transistor N
2
A are formed of the common conductive layer.
Drain
105
a
2
of driver transistor N
2
A, drain
105
b
1
of load transistor P
2
A and respective gates
107
c
of load transistor P
1
A and driver transistor N
1
A are electrically connected by means of a conductive layer
112
. Drain
105
a
2
of driver transistor N
1
A, drain
105
b
1
of load transistor P
1
A and respective gates
107
b
of load transistor P
2
A and driver transistor N
2
A are electrically connected by means of a conductive layer
112
.
In addition, conductive layer
112
which is electrically connected to source
105
a
3
of driver transistor N
2
A and conductive layer
112
which is electrically connected to source
105
a
3
of driver transistor N
1
A are electrically connected by means of a conductive layer
114
serving as a GND potential. In addition, both source
105
b
2
of load transistor P
1
A and source
105
b
2
of load transistor P
2
A are electrically connected to conductive layer
114
serving as a VDD potential. In addition, drain
105
a
1
of access transistor N
3
A is electrically connected to bit line BL while drain
105
a
1
of access transistors N
4
A is electrically connected to bit line/BL.
Memory cell MC
1
has approximately the same configuration as that of the above described memory cell MC
0
.
Driver transistors N
1
A and N
2
A and access transistors N
3
A and N
4
A of this memory cell MC
0
as well as driver transistors N
1
B and N
2
B and access transistors N
3
B and N
4
B of memory cell MC
1
are formed within common p-type well
103
. In addition, respective drains
105
b
1
and respective sources
105
b
2
of load transistors P
1
A and P
2
A of memory cell MC
0
as well as respective drains
105
b
1
and respective sources
105
b
2
of load transistors P
1
B and P
2
B of memory cell MC
1
are formed within common n-type well
102
.
As the memory cells are miniaturized, a problem with a soft error, that data hold in a storage node is inverted due to electrons generated by &agr; rays emitted from a package or due to neutron rays from space, becomes evident. In particular, this malfunction becomes evident as the power supply voltage is lowered.
One of the causes that invert the data hold in a storage node is the collection of a large number of electron hole pairs generated within a well by &agr; rays or neutron rays in an impurity region forming a storage node, changing the potential thereof. Electrons from among electron hole pairs generated within a p-type well are collected in an n-type impurity region within the same p-type well, thereby the potential of this n-type impurity region tends be lowered. In addition, holes among electron hole pairs generated within an n-type well are collected in a p-type impurity region within the same n-type well, thereby the potential of this p-type impurity region tends be raised. In the case that this p-type impurity region or n-type impurity region is a memory node, a so-called soft error generates, which the hold data is inverted by change in potential due to the collected electrons or holes.
In order to avoid the above described problem with soft errors, a variety of measures such that a capacitor is attached to a memory node so as to make it difficult to be inverted have been carried out up to the present. However, as miniaturization has progressed, the lowering of voltage has progressed and the capacitance of a memory node has become increasingly smaller. Therefore, circumstances have become such that an increase in area in order to attach a capacitor so as to prevent inversion cannot be avoided. For example, the capacitance of a memory node of an SRAM memory cell in the 0.18 &mgr;m generation is appro

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