Ultra small-sized SOI MOSFET and method of fabricating the same

Details Ultra small-sized SOI MOSFET and method of fabricating the same Ultra small-sized SOI MOSFET and method of fabricating the same

2002-12-31

2004-04-20

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S153000, C438S154000, C438S197000, C438S542000, C438S558000, C438S559000, C438S563000

Reexamination Certificate

active

06723587

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a metal oxide semiconductor field effect transistor (MOSFET), and more particularly, to an ultra small-sized SOI MOSFET and a method of fabricating the same.
2. Description of the Related Art
The size of silicon semiconductor devices has been decreasing more and more so as to meet the needs of low power consumption, high integration density, and high-speed operation. In particular, metal oxide semiconductor field effect transistors (MOSFETs) have been strongly required to have shorter channels, shallower junctions in source and drain regions, and thinner gate dielectric layers. Furthermore, semiconductor devices must be manufactured to have high performances by increasing the driving current while decreasing the leakage current. According to a conventional method of manufacturing a MOSFET, a gate dielectric layer is formed on a monocrystalline silicon substrate where an isolation region has already been formed to surround an activated region of a semiconductor device, and a conductive layer and a dielectric mask layer are sequentially deposited on the gate dielectric layer. Next, a gate electrode pattern is formed performing photolithography on the conductive layer and the dielectric mask layer. Next, impurity ions are implanted into the substrate using the gate electrode pattern as an ion implantation mask, and an interlayer dielectric layer is formed on the entire surface of the substrate. Next, contact holes are formed to expose a source region, a drain region, and a gate electrode, and a MOS transistor is completely formed using a metal wiring process.
Junction isolation in a bulk silicon substrate, which has been used to manufacture such a conventional silicon integrated circuit, may cause junction breakdown in a case where a pressure of about ±30 V is supplied under conventional doping levels and dimensions. Accordingly, junction isolation is not appropriate for high voltage applications. In addition, junction isolation is not effective in a high radioactive environment because of transient photocurrent generated in a pn junction by gamma rays. In order to overcome the disadvantages of junction isolation, a silicon on insulator (SOI) technique, by which a device is completely surrounded not by a pn junction but by an insulator, has been developed. A circuit manufactured using a SOI substrate can have a smaller size and a simpler structure than a circuit manufactured using a bulk silicon substrate. In addition, it is much simpler to manufacture a circuit using such a SOI technique. This technique still has another advantage: the operation speed of a circuit manufactured using this technique is fast due to the decrease in parasitic capacitance. However, even though such a SOI substrate is used, a MOS transistor has been manufactured in the conventional way in which source and drain regions are formed using ion implantation after formation of gate electrode patterns, as described above.
However, there are a lot of limits in manufacturing an ultra small-sized silicon device having high performances, using the conventional method of manufacturing a MOS transistor. In order to manufacture an ultra small-sized device having channels of several nano meters on a plane which is a conventional device structure, new techniques for forming patterns, such as direct patterning using electron beams, EUV exposure, or X-ray exposure, must be used. Accordingly, the manufacturing costs of silicon devices increase, and the mass production of silicon devices becomes more difficult.
In addition, it is very difficult to form very shallow junctions using conventional techniques for forming source and drain regions, such as ion implantation or plasma doping. A substrate may be damaged during ion implantation, which deteriorates the characteristics of a device. In addition, an expensive junction forming apparatus is necessary. In addition, as the size of devices becomes smaller, a problem of the conventional junction forming techniques with gate leakage current, which is caused due to the decrease in the thickness of a gate oxide layer, becomes more serious. In order to solve these problems, research has been carried out on a method of using a high dielectric material as a gate dielectric layer. However, in the conventional techniques, source and drain regions are formed after a gate dielectric layer is formed, and thus there is a limit in a subsequent activation heat treatment process.
Therefore, a new method of fabricating an ultra small-sized device is required to realize an integrated circuit having a high integration density and high performances.
SUMMARY OF THE INVENTION
To solve the above and other problems, it is an aspect of the present invention to provide an ultra small-sized SOI MOSFET, which has high reliability and a high integration density, and a method of fabricating the same.
To achieve the above aspect of the present invention, there is provided a method of fabricating an ultra small-sized SOI MOSFET. The method includes preparing a SOI substrate on which a monocrystalline silicon layer is formed, forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate, forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer, forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening, forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment, forming a gate dielectric layer in the opening on the channel region, forming a gate electrode on the gate dielectric layer to fit in the opening, forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed, forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer, and forming metal interconnections to bury the contact holes.
Preferably, the first material layer doped with the first conductivity-type impurities is a silicon oxide layer.
Preferably, the method may further include forming an oxide layer or a nitride layer on the first dielectric layer before the formation of the opening on the first dielectric material layer.
Preferably, the opening is formed in the first dielectric material layer using dry etching in order to control an etching angle, and thus the width of the opening is gradually decreasing toward a bottom surface of the dielectric material layer. Preferably, the sidewall of the opening and the top surface of the monocrystalline silicon layer forms an angle of no greater than 90° so as to reduce the length of the channel region.
Preferably, the source and drain regions are formed using rapid heat treatment so that they can contact the bottom surface of the monocrystalline silicon layer of the SOI substrate. Alternatively, the source and drain regions may be formed in the monocrystalline silicon layer so that there exists a predetermined distance between the bottom of the source and drain regions and the bottom surface of the monocrystalline silicon layer.
Preferably, the gate dielectric layer is formed of any of a silicon oxide layer thermally oxidized at low temperatures, an ozone oxide layer, a silicon nitride or silicon oxide layer deposited using CVD, and a high dielectric layer.
To achieve the above aspect of the present invention, there is provided an ultra small-sized SOI MOSFET manufactured using the aforementioned method.
Preferably, the first dielectric material layer doped with the first conductivity-type impurities is a silicon oxide layer. The gate electrode may be formed of polysilicon or any conductive materials.
Preferably, the opening is formed in the first dielectric material layer so that the width of the opening is gradually decreasing toward a bottom surface of the dielec

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