Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Solder wettable contact – lead – or bond
Reexamination Certificate
2000-10-18
2004-03-02
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Solder wettable contact, lead, or bond
C257S780000, C257S781000, C257S784000, C257S786000
Reexamination Certificate
active
06700208
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a surface mounting structure and, more particularly, to a surface mounting substrate having a plurality of bonding pads arranged in a staggered arrangement.
In recent years, densification and miniaturization of semiconductor chips have rapidly advanced, and, thereby, the number of connection terminals provided on a semiconductor chip has been increased. Accordingly, a distance between adjacent connection terminals has been reduced. Since the number of connection terminals is increased, the connection terminals are arranged along two rows in a staggered relationship so as to make a distance between the adjacent connection terminals as large as possible.
In order to attempt miniaturization of electronic equipment in which a semiconductor chip is incorporated, a mounting area of a mounting substrate on which a semiconductor chip is mounted must be reduced. Thus, a semiconductor chip is flip-chip mounted to a mounting substrate by using protruding electrodes (bumps) as the connection terminals of the semiconductor chip. Additionally, in order to achieve a package allowing a large power consumption and high-frequency characteristic, a surface mounting method such as the flip-chip mounting method is indispensable.
Additionally, the arrangement of the connection terminals has been shifted from a single row peripheral arrangement to a double row peripheral arrangement and further to an area bump arrangement so as to increase the number of the connection terminals. However, the area bump arrangement requires changes in the chip manufacturing process performed by a chip manufacturer such that redistribution of bonding pads and formation of solder bumps must be made by the chip manufacturer. That is, in order to introduce the flip-chip mounting method according to the area bump arrangement, a large change is needed not only in the design of the semiconductor chip but also in the manufacturing facility. Accordingly, it is difficult to shift to the area bump arrangement in a short period of time.
On the other hand, since there is no large change in mounting processes between a semiconductor chip provided with connection terminals in the double row peripheral arrangement and a semiconductor chip provided with connection terminals provided in the single row peripheral arrangement, merely a design change may be sufficient to shift from the single row peripheral arrangement to the double row peripheral arrangement. Accordingly, use of semiconductor chips which adopts the double row peripheral arrangement increases so as to deal with the increase in the connection terminals of the recent semiconductor chips.
2. Description of the Related Art
FIG. 1
is a plan view of a semiconductor chip having protruding electrodes in the double row peripheral arrangement. The semiconductor chip
1
shown in
FIG. 1
is configured and arranged to be mounted to a mounting substrate by a flip-chip mounting method. The protruding electrodes
2
are formed as stud bumps
2
made of gold. The gold bumps
2
are arranged in two rows in the surroundings of the mounting area of the semiconductor chip
1
.
FIG. 2
is a plan view of a mounting substrate to which the semiconductor chip
1
shown in
FIG. 1
is mounted. Bonding pads
4
are provided on a wiring surface of the mounting substrate
3
in positions corresponding to the arrangement of the gold bumps
2
of the semiconductor chip
1
. A conductive wiring part
5
extends from each of the bonding pads
4
so that each of the bonding pads
4
is connected to a corresponding one of interlayer connection pads
6
. In
FIG. 2
, the semiconductor chip
1
is to be mounted in an area indicated by single dashed chain lines, and the gold bumps
2
are to be soldered to the corresponding bonding pads
4
.
Solder resist is applied to hatched areas in
FIG. 2
so that solder is not applied to the hatched areas when the solder is applied to the bonding pads
4
. Each of the bonding pads
4
and a part of each of the conductive wiring parts
5
are located in the area where the solder resist is not applied so as to be provided with the solder during the solder applying process.
Japanese Laid-Open Patent Application No. 11-145328 discloses a technique to bond bumps formed on a semiconductor chip to pad portions of conductive wiring members by an electrically conductive adhesive. The bumps of the semiconductor chip are arranged in a staggered arrangement of two rows, and the pad portions of the substrate are also arranged in a staggered arrangement of two rows. A conductive wiring part having a width smaller than the width of the pad extends from an end of each of the pad portions arranged on one of the two rows and protrudes into an area between adjacent two pad portions arranged on the other one of the two rows.
The semiconductor chip having the protruding bumps in the double row peripheral arrangement is originally designed to be mounted to a mounting substrate by a wire bonding method. Accordingly, a distance between the two rows of the protruding electrodes is as small as 100 &mgr;m to 150 &mgr;m. Thus, when the thus-designed semiconductor chip is mounted on a substrate by a flip-chip mounting method, each of the protruding electrodes of the semiconductor chip must be bonded to an extreme end of the corresponding one of the pad portions.
FIG. 3
is an enlarged plan view of a portion of the mounting substrate
3
shown in
FIG. 2
which portion includes the bonding pads
4
. In
FIG. 3
, areas indicated by dotted lines are areas where the gold bumps
2
of the semiconductor chip
1
are bonded. The conductive wiring patterns are formed by etching a copper plate on the mounting substrate
3
. According to the recent technique, a distance between adjacent ones of the conductive wiring patterns is required to be at least about 40 &mgr;m. Additionally, a diameter of each of the gold bumps is 80 &mgr;m. Accordingly, if the distance between the two rows along which the bonding pads are arranged is set to a minimum value which is about 40 &mgr;m, a portion of each of the gold bumps protrudes from the corresponding one of the bonding pads
4
. Thus, in a case in which the gold bumps
2
are offset in the longitudinal direction of the bonding pads
4
due to a positioning error, a large portion of each of the gold bumps
2
is out of the corresponding one of the bonding pads
4
.
Additionally, if each of the bonding pads
4
has an elongated rectangular shape as shown in
FIG. 3
, the gold bumps
2
may not be sufficiently bonded to the bonding pads
4
. A description will now be given, with reference to
FIGS. 4A and 4B
, of a case in which an incomplete bonding occurs.
FIG. 4A
is a cross-sectional view showing a state in which the gold bump
2
is located at an accurate position relative to the bonding pad
4
.
FIG. 4B
is a cross-sectional view showing a state in which the gold bump
2
is offset from the accurate position on the bonding pad
4
. It should be noted that each of
FIGS. 4A and 4B
corresponds to a cross-sectional view taken along a line IV—IV of FIG.
3
.
When the semiconductor chip
1
is mounted to the mounting substrate
3
by a flip-chip bonding method, a solder
7
is previously applied to each of the bonding pads
4
. The solder
7
on each of the bonding pads
4
has a maximum thickness in the middle thereof and the thickness is reduced toward each end of each of the bonding pads
4
. Such a shape of the solder
7
is caused by the surface tension of the melted solder
7
. Accordingly, the solder
7
on each of the bonding pads
4
solidifies in the thus-formed state.
When the gold bump
2
is located at a normal position as shown in
FIG. 4A
, the gold bump
2
is bonded at a position where the solder
7
is relatively thick. Thus, the gold bump
2
is normally soldered to the bonding pad
4
by a sufficient amount of solder. On the other hand, when the gold bump
3
is offset from the normal position in the longitudinal direction of the bonding pad
4
as
Ladas & Parry
Shinko Electric Industries Co. Ltd.
Soward Ida M.
Zarabian Amir
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