Clock controlling method and clock control circuit

Details Clock controlling method and clock control circuit Clock controlling method and clock control circuit

2001-11-14

2004-05-25

Huynh, Kim (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S401000, C713S501000, C713S502000, C713S503000, C713S600000, C716S030000, C716S030000, C716S030000, C716S030000, C327S158000, C327S291000, C327S292000, C327S295000

Reexamination Certificate

active

06742133

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a clock controlling method and a clock control circuit. More particularly, it relates to a clock controlling method and a clock control circuit convenient for generating a clock signal having a multiplied frequency of an external clock and being synchronized with the external clock.
BACKGROUND OF THE INVENTION
Recently, with an increasing size of circuits that can be integrated on one chip and with an increasing operating frequency, a clock control circuit has come to be used for controlling the phase and frequency of clock inside and outside a chip of a semiconductor integrated circuit including a synchronization circuit operating on a clock signal supplied to the circuit.
As a clock control circuit, a feedback type circuit, such as a PLL (phase locked loop) or a DLL (delay synchronization loop), has so far been used. Of these, the PLL circuit is made up of a phase comparator circuit receiving a reference clock signal as an input, a charge pump for charging and discharging a capacitor to generate a voltage corresponding to a phase difference output from the phase comparator circuit, a loop filter for smoothing a voltage corresponding to the phase difference, a voltage controlled oscillator receiving a voltage output from the loop filter as a control voltage to vary an oscillation frequency responsive to the control voltage, and a frequency divider for frequency dividing an oscillation output signal from the voltage controlled oscillator to provide a frequency divided signal to the phase comparator circuit. The phase comparator circuit compares the phase difference between the reference clock signal and the signal output from the frequency divider to control the oscillation frequency of the voltage controlled oscillator responsive to the result of phase comparison and hence the voltage controlled oscillator is made to output a clock signal which is phase-synchronized with the reference clock signal which is provided to the phase comparator circuit.
As a circuit for frequency multiplying an input clock, a circuit comprised of the combination of a PLL circuit and an interpolator (interior division circuit) is known in the art. See, for example, Publication 1 (ISSC 1993 p.p. 160-161, Mark Horowitz et al., “PLL Design for 500 MHz Interface”). Meanwhile, the interpolator disclosed in this Publication 1 is of an analog circuit configuration made up of a differential circuit receiving two inputs.
As is well-known, the configuration employing a PLL circuit suffers from the problem that phase synchronization is extremely time-consuming, and that there persists phase jitter ascribable to a feedback loop and marked phase shifting is produced in case the locked state is disengaged due to such jitter.
As a non-feedback type frequency multiplied clock generating circuit, not employing the feedback system, such as PLL, the present inventors have already proposed a construction in e.g., JP Patent Application No. 11-004145, as shown in
FIGS. 12
to
15
hereof. Referring to
FIG. 12
, this multiplier circuit includes a frequency divider
2
for dividing the frequency of the input clock
1
to generate multi-phase clocks
3
, a multi-phase clock multiplier circuit
5
, which receives output
3
from the frequency divider
2
, as an input, a period detection circuit
6
, made up of a ring oscillator of a fixed number of stages and a counter for counting the number of times of oscillations of the ring oscillator during one clock period of the input clock
1
to detect the period of the clock
1
to output a control signal
7
, and a clock synthesis circuit
8
for synthesizing the output signal of the multi-phase clock multiplier circuit
5
to generate a frequency multiplied clock signal. The multi-phase clock multiplier circuit
5
includes plural timing difference division circuits
4
a
for outputting signals corresponding to the interior division of the timing difference (phase difference) of two inputs and plural multiplexing circuits
4
b
for multiplexing output signals of two of the timing difference division circuits.
The plural timing difference division circuits
4
a
are comprised of plural timing difference division circuits which receives clock signals of the same phase as inputs, and plural timing difference division circuits which receives two neighboring clock signals. The period detection circuit
6
outputs a control signal
7
to adjust the load capacitance of the timing difference division circuits
4
a
in the multi-phase clock multiplier circuit
5
to control the clock period.
FIG. 13
shows, as an example of the clock multiplier circuit, a specified illustrative structure of a four-phase clock multiplier circuit for generating four-phase clocks. Referring to
FIG. 13
, the four-phase clock multiplier circuit includes a ¼ frequency divider circuit
201
for frequency dividing an input clock
205
by four to output four-phase clocks Q
1
to Q
4
, a n-stage cascaded connection of four-phase clock multiplier circuits
202
1
to
202
n
, a clock synthesis circuit
203
and a period detection circuit
204
. The last stage four-phase clock multiplier circuit
202
n
outputs 2n-multiplied four-phase clocks Qn
1
to Qn
4
, which are synthesized in the clock synthesis circuit
203
so as to be output as a multiplied clock signal
207
. Meanwhile, the number of stage n of the four-phase clock multiplier circuits is arbitrary.
The
¼ frequency divider 201 frequency divides the input clock 205 by four to generate four-phase clocks Q1 to Q4 which are then multiplied by the four-phase clock multiplier circuit 202
1
to generate four-phase clocks Q
11
to Q
14
. In similar manner, 2n-tupled four-phase clocks Qn
1
to Qn
4
are produced from the four-phase clock multiplier circuit
202
n
.
The period detection circuit
204
is made up of a ring oscillator having a fixed number of stages and a counter. During the periods of the clocks
205
, the number of times of oscillations of the ring oscillator is counted by the counter to output control signals
206
depending on the number of counts to adjust the load in the four-phase clock multiplier circuit
202
. This period detection circuit
204
resolves fluctuations in device characteristics during the clock period operation.
The operation of the four-phase clock multiplier circuit
202
is explained. The four-phase clocks are converted into eight phase clocks by the four-phase lock multiplier circuit
202
of FIG.
13
and converted back to four-phase clocks to effect multiplication continuously, as now explained in detail.
FIG. 14
shows an illustrative structure of the four-phase clock multiplier circuit
202
n
shown in FIG.
13
. Meanwhile, the four-phase clock multiplier circuits
202
1
to
202
n
are of the same structure.
Referring to
FIG. 14
a
, this four-phase clock multiplier circuit
202
n
is made up of eight sets of timing difference division circuits
208
to
215
, eight sets of pulse width correction circuits
216
to
223
and four sets of multiplexer circuits
224
to
227
.
FIG. 14
b
shows the structure of a pulse width correction circuit comprised of a NAND circuit receiving signals corresponding to the second input T
23
inverted by an inverter INV and the first input T
21
, as inputs.
FIG. 14
c
shows the structure of a multiplier circuit comprised of a two-input AND circuit.
FIG. 15
shows a signal waveform diagram for illustrating the timing operation of the four-phase clock multiplier circuit
202
shown in FIG.
14
. The rising of the clock T
21
is determined by a delay corresponding to the internal delay of the timing difference division circuit
208
as from the rising of the clock Q(n−1)
1
, the rising of the clock T
22
is determined by timing division by a timing difference division circuit
209
of the timing difference between the rise timing of the clock Q(n−1)1 and the rise of the clock Q(n−1)
2
and by the delay corresponding to the internal delay, and the rise timing of the clock T
23
is determined by the timing di

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