Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-08-12
2004-05-18
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06738956
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a circuit configuration of a chip and, more particularly to a circuit configuration of a chip with a graphic controller integrated and a method for testing such a circuit configuration, in which a test circuit is employed in a main control module such that a graphic controller is directly connected to a plurality of buses in a testing mode. In this manner, a plurality of testing requests are transmitted to the graphic controller by using frequency multiplying modes and the required pin count for testing is lowered by using at least one multiplexer and one latch at the memory end.
2. Description of the Prior Art
In recent years, with the high development in information-related industries and the trend that the electronic products are continuously downsized, more and more electronic devices have been successfully integrated on one chip. Conventionally, a graphic chip is fabricated as an independent chip since the great amount of employed devices may occupy a large area. However, with the tremendous improvement in semiconductor processing technology, it is no more difficult to integrate such a graphic chip and the north bridge circuit on one chip. This has attracted lots of attention from the industries.
A number of testing processes are necessary for any of the newly designed products to examine if the features provided by such devices can function normally according to the specifications. In general, the circuit configuration of a north bridge chip with integrated graphic functions is shown as in
FIG. 1
, which comprises: a graphic controller
181
and a north bridge circuit
183
. The north bridge circuit
183
includes a front side bus (FSB) controller
182
, a memory controller
184
and a peripheral component interconnect (PCI) controller
186
. More particularly, the FSB controller
182
is connected through a front side bus
125
to a central process unit (CPU)
12
. The memory controller
184
is connected through a memory bus
145
to a memory
14
. The PCI controller
186
is connected to a plurality of peripheral components through a PCI bus
185
. The graphic controller
181
is connected to a displayer
16
. When an integrated chip
18
is to be tested, a series of testing requests corresponding to the items to be tested are input into the integrated chip
18
. Then the results from the displayer
16
and the memory
14
are compared to the expected values to determine whether the design of the product is perfect.
Nevertheless, the state-of-the-art information technology improves with each passing day. Most of the interface specifications that were ever popular have gradually been replaced by the newer ones. For example, the specifications related to the north bridge circuit
183
include a wide range (such as FSBs of various frequency of clock specifications, PCI bus interconnections and V-link interconnections between the north bridge and the south bridge, and interconnections for memories of various specifications) and are updated very fast. On the contrary, the graphic controller
181
changes relatively slowly in its specifications. In average, as the graphic controller specification is updated once, the north bridge specification may have been updated five times. However, the circuit configuration of the conventional integrated chip as well as its testing method cannot allow the testing of the graphic controller to be independent of the north bridge circuit. For a newly designed integrated chip that comprises the same graphic controller and a different north bridge in specification, the entire testing process is required to repeat for the change in the north bridge so as to obtain the values for comparison. However, it takes 6 to 8 months to obtain a set of such values, which is time-consuming and disadvantageous for a new product. On the other hand, the downsized chip results in a lower pin count, which leads to an insufficient pin count for the testing of the graphic controller.
Therefore, there is need in providing a circuit configuration of a chip with a graphic controller integrated and a method for testing such a circuit configuration in view of the above problems such that the testing procedures for the graphic controller and the north bridge circuit can be separated, the required pin count for testing is lowered, the testing data can be reused, and the time consumed for testing can be shortened.
SUMMARY OF THE INVENTION
Accordingly, it is the primary object of the present invention to provide a circuit configuration of a chip with a graphic controller integrated, in which a test circuit is employed in a main control module such that a graphic controller is directly connected to a plurality of buses through the test circuit in a testing mode.
It is another object of the present invention to provide a circuit configuration of a chip with a graphic controller integrated, in which the test circuit further comprises a frequency converter for converting the clock frequency for data transmission between a front side bus and the graphic controller.
It is still another object of the present invention to provide a circuit configuration of a chip with a graphic controller integrated, in which the test circuit further comprises at least one multiplexer so as to lower the required pin count between the graphic controller and the buses.
It is still another object of the present invention to provide a method for testing a circuit configuration, in which a plurality of testing requests are transmitted to the test circuit by using a frequency multiplying mode and then converted into a single-frequency mode transmitted to the graphic controller so as to lower the pin count needed for testing.
In order to achieve the foregoing objects, the present invention provides a circuit configuration of a chip with a graphic controller integrated, comprising: a main control module, including at least one front side bus (FSB) controller connected through a front side bus to a central process unit (CPU) and a memory controller connected through a memory bus to a memory; a graphic controller, for processing the requests and operation for a graphic display, an accelerated graphic port and a graphic engine; and a test circuit, installed in said main control module so as to allow said graphic controller to be directly connected to said buses through said test circuit in a testing mode; wherein, in said testing mode, said test circuit processes a plurality of testing data at a rate which is a plurality of times the data transmission rate of said graphic controller.
The present invention further provides a method for testing a circuit configuration, comprising steps of: providing a plurality of testing requests and a plurality of testing data corresponding to said testing requests; activating a testing mode so as to allow a graphic controller to be connected through a test circuit to a front side bus and a memory bus; transmitting said testing requests to said graphic controller through said test circuit by using said front side bus; and obtaining tested results of said graphic controller by comparing said testing data corresponding to said testing requests.
Other and further features, advantages and benefits of the invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and following detailed description are exemplary and explanatory but are not to be restrictive of the invention. The accompanying drawings are incorporated in and constitute a part of this application and, together with the description, serve to explain the principles of the invention in general terms. Like numerals refer to like parts throughout the disclosure.
REFERENCES:
patent: 5650955 (1997-07-01), Puar et al.
patent: 5678009 (1997-10-01), Bains et al.
patent: 5920881 (1999-07-01), Porterfield
patent: 5991833 (1999-11-01), Wandler et al.
patent: 6101566 (2000-08-01), Woods et al.
patent: 6192457 (2001-02-
Lin Jiing
Tang Kuang-Yu
Wang Hsuan-Yi
Wu Chun-Yi
Lin Sun James
Rosenberg , Klein & Lee
Smith Matthew
Via Technologies Inc.
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